mirror of
https://github.com/AsahiLinux/u-boot
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9c7fbebe5d
8ULP ROM should read the LPOSC trim BIAS fuse to fill the CGC0 LPOSCCTRL[7:0], but it writes a fixed value on A0.1 revision. A0.2 will fix the issue in ROM. But A0.1 we have to workaround it in SPL by setting LPOSCCTRL BIASCURRENT again. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
114 lines
2.2 KiB
C
114 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2021 NXP
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*/
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#include <common.h>
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#include <init.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8ulp-pins.h>
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#include <dm/uclass.h>
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#include <dm/device.h>
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#include <dm/uclass-internal.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/rdc.h>
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#include <asm/arch/upower.h>
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DECLARE_GLOBAL_DATA_PTR;
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void spl_dram_init(void)
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{
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init_clk_ddr();
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ddr_init(&dram_timing);
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}
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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int power_init_board(void)
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{
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u32 pmic_reg;
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/* PMIC set bucks1-4 to PWM mode */
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upower_pmic_i2c_read(0x10, &pmic_reg);
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upower_pmic_i2c_read(0x14, &pmic_reg);
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upower_pmic_i2c_read(0x21, &pmic_reg);
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upower_pmic_i2c_read(0x2e, &pmic_reg);
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upower_pmic_i2c_write(0x10, 0x3d);
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upower_pmic_i2c_write(0x14, 0x7d);
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upower_pmic_i2c_write(0x21, 0x7d);
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upower_pmic_i2c_write(0x2e, 0x3d);
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upower_pmic_i2c_read(0x10, &pmic_reg);
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upower_pmic_i2c_read(0x14, &pmic_reg);
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upower_pmic_i2c_read(0x21, &pmic_reg);
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upower_pmic_i2c_read(0x2e, &pmic_reg);
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/* Set buck3 to 1.1v OD */
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upower_pmic_i2c_write(0x22, 0x28);
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return 0;
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}
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void spl_board_init(void)
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{
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struct udevice *dev;
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uclass_find_first_device(UCLASS_MISC, &dev);
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for (; dev; uclass_find_next_device(&dev)) {
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if (device_probe(dev))
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continue;
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}
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board_early_init_f();
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preloader_console_init();
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puts("Normal Boot\n");
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/* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */
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/* Load the lposc fuse for single boot to work around ROM issue,
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* The fuse depends on S400 to read.
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*/
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if (is_soc_rev(CHIP_REV_1_0) && get_boot_mode() == SINGLE_BOOT)
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load_lposc_fuse();
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upower_init();
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power_init_board();
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/* DDR initialization */
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spl_dram_init();
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/* This must place after upower init, so access to MDA and MRC are valid */
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/* Init XRDC MDA */
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xrdc_init_mda();
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/* Init XRDC MRC for VIDEO, DSP domains */
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xrdc_init_mrc();
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/* Call it after PS16 power up */
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set_lpav_qos();
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}
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void board_init_f(ulong dummy)
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{
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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timer_init();
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arch_cpu_init();
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board_init_r(NULL, 0);
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}
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