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u-boot/arch/arm/cpu/armv8
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Bhupesh Sharma 9c66ce662c fsl-ch3/lowlevel: TZPC and TZASC programming to configure non-secure accesses 
This patch ensures that the TZPC (BP147) and TZASC-400 programming
happens for LS2085A SoC only when the desired config flags are
enabled and ensures that the TZPC programming is done to allow Non-secure
(NS) + secure (S) transactions only for DCGF registers.

The TZASC component is not present on LS2085A-Rev1, so the TZASC-400
config flag is turned OFF for now.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:08:06 -08:00
..
fsl-lsch3 fsl-ch3/lowlevel: TZPC and TZASC programming to configure non-secure accesses 2015-02-24 13:08:06 -08:00
cache.S ARM: armv8: Fix typo in commentary 2015-01-14 11:37:39 -05:00
cache_v8.c ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC 2014-07-03 08:40:51 +02:00
config.mk arm: Switch to -mno-unaligned-access when supported by the compiler 2014-02-26 21:19:32 +01:00
cpu.c arm64: core support 2014-01-09 16:08:44 +01:00
exceptions.S arm64: core support 2014-01-09 16:08:44 +01:00
generic_timer.c arm64: core support 2014-01-09 16:08:44 +01:00
Makefile kbuild: use SoC-specific CONFIG to descend into SoC directory 2014-11-23 06:49:02 -05:00
start.S Arm64 fix a bug of vbar_el3 initialization 2014-05-25 15:26:00 +02:00
tlb.S arm64: core support 2014-01-09 16:08:44 +01:00
transition.S armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page 2014-09-25 08:36:19 -07:00
u-boot.lds arm64: core support 2014-01-09 16:08:44 +01:00