mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 19:10:13 +00:00
95e9a8e2cb
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - SPL not supported yet --> no spl-directory in arch/arm/mach-nexell. Appropriate line in Makefile removed. - clock.c: 'section(".data")' added to declaration of clk_periphs[] and core_hz. - Kconfig: Changes to have a structure like in mach-bcm283x/Kconfig, e.g. "config ..." entries moved from other Kconfig. - timer.c: 'section(".data")' added to declaration of timestamp and lastdec. - arch/arm/mach-nexell/serial.c removed because this is for the UARTs of the S5P6818 SoC which is not supported yet. S5P4418 UARTs are different, here the (existing) PL011-code is used. - '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where possible (and similar). Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
352 lines
9.6 KiB
C
352 lines
9.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Nexell
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* Youngbok, Park <ybpark@nexell.co.kr>
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*/
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/*
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* FIXME : will be remove after support pinctrl
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*/
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#include <linux/types.h>
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#include <asm/io.h>
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#include <asm/arch/nexell.h>
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#include "asm/arch/nx_gpio.h"
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#define NUMBER_OF_GPIO_MODULE 5
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u32 __g_nx_gpio_valid_bit[NUMBER_OF_GPIO_MODULE] = {
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF};
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static struct {
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struct nx_gpio_register_set *pregister;
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} __g_module_variables[NUMBER_OF_GPIO_MODULE] = {
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{ (struct nx_gpio_register_set *)PHY_BASEADDR_GPIOA },
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{ (struct nx_gpio_register_set *)PHY_BASEADDR_GPIOB },
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{ (struct nx_gpio_register_set *)PHY_BASEADDR_GPIOC },
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{ (struct nx_gpio_register_set *)PHY_BASEADDR_GPIOD },
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{ (struct nx_gpio_register_set *)PHY_BASEADDR_GPIOE },
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};
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enum { nx_gpio_max_bit = 32 };
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void nx_gpio_set_bit(u32 *value, u32 bit, int enable)
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{
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register u32 newvalue;
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newvalue = *value;
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newvalue &= ~(1ul << bit);
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newvalue |= (u32)enable << bit;
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writel(newvalue, value);
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}
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int nx_gpio_get_bit(u32 value, u32 bit)
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{
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return (int)((value >> bit) & (1ul));
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}
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void nx_gpio_set_bit2(u32 *value, u32 bit, u32 bit_value)
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{
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register u32 newvalue = *value;
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newvalue = (u32)(newvalue & ~(3ul << (bit * 2)));
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newvalue = (u32)(newvalue | (bit_value << (bit * 2)));
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writel(newvalue, value);
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}
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u32 nx_gpio_get_bit2(u32 value, u32 bit)
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{
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return (u32)((u32)(value >> (bit * 2)) & 3ul);
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}
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int nx_gpio_initialize(void)
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{
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static int binit;
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u32 i;
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binit = 0;
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if (binit == 0) {
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for (i = 0; i < NUMBER_OF_GPIO_MODULE; i++)
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__g_module_variables[i].pregister = NULL;
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binit = true;
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}
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for (i = 0; i < NUMBER_OF_GPIO_MODULE; i++) {
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__g_nx_gpio_valid_bit[i] = 0xFFFFFFFF;
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};
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return true;
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}
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u32 nx_gpio_get_number_of_module(void)
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{
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return NUMBER_OF_GPIO_MODULE;
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}
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u32 nx_gpio_get_size_of_register_set(void)
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{
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return sizeof(struct nx_gpio_register_set);
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}
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void nx_gpio_set_base_address(u32 module_index, void *base_address)
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{
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__g_module_variables[module_index].pregister =
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(struct nx_gpio_register_set *)base_address;
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}
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void *nx_gpio_get_base_address(u32 module_index)
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{
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return (void *)__g_module_variables[module_index].pregister;
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}
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int nx_gpio_open_module(u32 module_index)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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writel(0xFFFFFFFF, &pregister->gpiox_slew_disable_default);
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writel(0xFFFFFFFF, &pregister->gpiox_drv1_disable_default);
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writel(0xFFFFFFFF, &pregister->gpiox_drv0_disable_default);
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writel(0xFFFFFFFF, &pregister->gpiox_pullsel_disable_default);
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writel(0xFFFFFFFF, &pregister->gpiox_pullenb_disable_default);
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return true;
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}
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int nx_gpio_close_module(u32 module_index) { return true; }
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int nx_gpio_check_busy(u32 module_index) { return false; }
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void nx_gpio_set_pad_function(u32 module_index, u32 bit_number,
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u32 padfunc)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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nx_gpio_set_bit2(&pregister->gpioxaltfn[bit_number / 16],
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bit_number % 16, padfunc);
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}
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void nx_gpio_set_pad_function32(u32 module_index, u32 msbvalue, u32 lsbvalue)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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writel(lsbvalue, &pregister->gpioxaltfn[0]);
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writel(msbvalue, &pregister->gpioxaltfn[1]);
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}
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int nx_gpio_get_pad_function(u32 module_index, u32 bit_number)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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return (int)nx_gpio_get_bit2
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(readl(&pregister->gpioxaltfn[bit_number / 16]),
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bit_number % 16);
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}
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void nx_gpio_set_output_enable(u32 module_index, u32 bit_number,
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int output_enb)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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nx_gpio_set_bit(&pregister->gpioxoutenb, bit_number, output_enb);
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}
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int nx_gpio_get_detect_enable(u32 module_index, u32 bit_number)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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return nx_gpio_get_bit(readl(&pregister->gpioxdetenb), bit_number);
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}
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u32 nx_gpio_get_detect_enable32(u32 module_index)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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return readl(&pregister->gpioxdetenb);
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}
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void nx_gpio_set_detect_enable(u32 module_index, u32 bit_number,
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int detect_enb)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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nx_gpio_set_bit(&pregister->gpioxdetenb, bit_number, detect_enb);
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}
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void nx_gpio_set_detect_enable32(u32 module_index, u32 enable_flag)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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writel(enable_flag, &pregister->gpioxdetenb);
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}
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int nx_gpio_get_output_enable(u32 module_index, u32 bit_number)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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return nx_gpio_get_bit(readl(&pregister->gpioxoutenb), bit_number);
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}
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void nx_gpio_set_output_enable32(u32 module_index, int output_enb)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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if (output_enb)
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writel(0xFFFFFFFF, &pregister->gpioxoutenb);
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else
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writel(0x0, &pregister->gpioxoutenb);
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}
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u32 nx_gpio_get_output_enable32(u32 module_index)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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return readl(&pregister->gpioxoutenb);
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}
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void nx_gpio_set_output_value(u32 module_index, u32 bit_number, int value)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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nx_gpio_set_bit(&pregister->gpioxout, bit_number, value);
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}
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int nx_gpio_get_output_value(u32 module_index, u32 bit_number)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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return nx_gpio_get_bit(readl(&pregister->gpioxout), bit_number);
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}
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void nx_gpio_set_output_value32(u32 module_index, u32 value)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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writel(value, &pregister->gpioxout);
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}
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u32 nx_gpio_get_output_value32(u32 module_index)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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return readl(&pregister->gpioxout);
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}
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int nx_gpio_get_input_value(u32 module_index, u32 bit_number)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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return nx_gpio_get_bit(readl(&pregister->gpioxpad), bit_number);
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}
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void nx_gpio_set_pull_select(u32 module_index, u32 bit_number, int enable)
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{
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nx_gpio_set_bit(&__g_module_variables[module_index]
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.pregister->gpiox_pullsel_disable_default,
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bit_number, true);
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nx_gpio_set_bit
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(&__g_module_variables[module_index].pregister->gpiox_pullsel,
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bit_number, enable);
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}
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void nx_gpio_set_pull_select32(u32 module_index, u32 value)
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{
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writel(value,
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&__g_module_variables[module_index].pregister->gpiox_pullsel);
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}
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int nx_gpio_get_pull_select(u32 module_index, u32 bit_number)
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{
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return nx_gpio_get_bit
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(__g_module_variables[module_index].pregister->gpiox_pullsel,
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bit_number);
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}
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u32 nx_gpio_get_pull_select32(u32 module_index)
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{
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return __g_module_variables[module_index].pregister->gpiox_pullsel;
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}
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void nx_gpio_set_pull_mode(u32 module_index, u32 bit_number, u32 mode)
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{
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nx_gpio_set_bit(&__g_module_variables[module_index]
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.pregister->gpiox_pullsel_disable_default,
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bit_number, true);
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nx_gpio_set_bit(&__g_module_variables[module_index]
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.pregister->gpiox_pullenb_disable_default,
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bit_number, true);
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if (mode == nx_gpio_pull_off) {
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nx_gpio_set_bit
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(&__g_module_variables[module_index].pregister->gpiox_pullenb,
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bit_number, false);
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nx_gpio_set_bit
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(&__g_module_variables[module_index].pregister->gpiox_pullsel,
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bit_number, false);
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} else {
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nx_gpio_set_bit
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(&__g_module_variables[module_index].pregister->gpiox_pullsel,
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bit_number, (mode & 1 ? true : false));
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nx_gpio_set_bit
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(&__g_module_variables[module_index].pregister->gpiox_pullenb,
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bit_number, true);
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}
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}
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void nx_gpio_set_fast_slew(u32 module_index, u32 bit_number,
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int enable)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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nx_gpio_set_bit(&pregister->gpiox_slew, bit_number,
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(int)(!enable));
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}
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void nx_gpio_set_drive_strength(u32 module_index, u32 bit_number,
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u32 drvstrength)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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nx_gpio_set_bit(&pregister->gpiox_drv1, bit_number,
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(int)(((u32)drvstrength >> 0) & 0x1));
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nx_gpio_set_bit(&pregister->gpiox_drv0, bit_number,
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(int)(((u32)drvstrength >> 1) & 0x1));
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}
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void nx_gpio_set_drive_strength_disable_default(u32 module_index,
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u32 bit_number, int enable)
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{
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register struct nx_gpio_register_set *pregister;
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pregister = __g_module_variables[module_index].pregister;
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nx_gpio_set_bit(&pregister->gpiox_drv1_disable_default, bit_number,
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(int)(enable));
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nx_gpio_set_bit(&pregister->gpiox_drv0_disable_default, bit_number,
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(int)(enable));
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}
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u32 nx_gpio_get_drive_strength(u32 module_index, u32 bit_number)
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{
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register struct nx_gpio_register_set *pregister;
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register u32 retvalue;
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pregister = __g_module_variables[module_index].pregister;
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retvalue =
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nx_gpio_get_bit(readl(&pregister->gpiox_drv0), bit_number) << 1;
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retvalue |=
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nx_gpio_get_bit(readl(&pregister->gpiox_drv1), bit_number) << 0;
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return retvalue;
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}
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