mirror of
https://github.com/AsahiLinux/u-boot
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401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
346 lines
7.3 KiB
C
346 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*/
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#include <config.h>
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#include <common.h>
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#include <init.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#if defined(CONFIG_ARCH_MVEBU)
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/* Use common XOR definitions for A3x and AXP */
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#include "../../../drivers/ddr/marvell/axp/xor.h"
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#include "../../../drivers/ddr/marvell/axp/xor_regs.h"
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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struct sdram_bank {
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u32 win_bar;
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u32 win_sz;
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};
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struct sdram_addr_dec {
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struct sdram_bank sdram_bank[4];
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};
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#define REG_CPUCS_WIN_ENABLE (1 << 0)
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#define REG_CPUCS_WIN_WR_PROTECT (1 << 1)
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#define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
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#define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
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#ifndef MVEBU_SDRAM_SIZE_MAX
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#define MVEBU_SDRAM_SIZE_MAX 0xc0000000
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#endif
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#define SCRUB_MAGIC 0xbeefdead
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#define SCRB_XOR_UNIT 0
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#define SCRB_XOR_CHAN 1
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#define SCRB_XOR_WIN 0
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#define XEBARX_BASE_OFFS 16
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/*
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* mvebu_sdram_bar - reads SDRAM Base Address Register
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*/
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u32 mvebu_sdram_bar(enum memory_bank bank)
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{
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struct sdram_addr_dec *base =
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(struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
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u32 result = 0;
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u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
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if ((!enable) || (bank > BANK3))
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return 0;
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result = readl(&base->sdram_bank[bank].win_bar);
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return result;
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}
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/*
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* mvebu_sdram_bs_set - writes SDRAM Bank size
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*/
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static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
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{
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struct sdram_addr_dec *base =
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(struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
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/* Read current register value */
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u32 reg = readl(&base->sdram_bank[bank].win_sz);
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/* Clear window size */
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reg &= ~REG_CPUCS_WIN_SIZE(0xFF);
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/* Set new window size */
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reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24);
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writel(reg, &base->sdram_bank[bank].win_sz);
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}
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/*
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* mvebu_sdram_bs - reads SDRAM Bank size
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*/
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u32 mvebu_sdram_bs(enum memory_bank bank)
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{
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struct sdram_addr_dec *base =
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(struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
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u32 result = 0;
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u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
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if ((!enable) || (bank > BANK3))
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return 0;
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result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
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result += 0x01000000;
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return result;
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}
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void mvebu_sdram_size_adjust(enum memory_bank bank)
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{
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u32 size;
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/* probe currently equipped RAM size */
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size = get_ram_size((void *)mvebu_sdram_bar(bank),
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mvebu_sdram_bs(bank));
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/* adjust SDRAM window size accordingly */
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mvebu_sdram_bs_set(bank, size);
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}
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#if defined(CONFIG_ARCH_MVEBU)
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static u32 xor_ctrl_save;
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static u32 xor_base_save;
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static u32 xor_mask_save;
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static void mv_xor_init2(u32 cs)
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{
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u32 reg, base, size, base2;
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u32 bank_attr[4] = { 0xe00, 0xd00, 0xb00, 0x700 };
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xor_ctrl_save = reg_read(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT,
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SCRB_XOR_CHAN));
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xor_base_save = reg_read(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT,
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SCRB_XOR_WIN));
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xor_mask_save = reg_read(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT,
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SCRB_XOR_WIN));
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/* Enable Window x for each CS */
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reg = 0x1;
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reg |= (0x3 << 16);
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reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), reg);
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base = 0;
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size = mvebu_sdram_bs(cs) - 1;
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if (size) {
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base2 = ((base / (64 << 10)) << XEBARX_BASE_OFFS) |
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bank_attr[cs];
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reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
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base2);
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base += size + 1;
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size = (size / (64 << 10)) << 16;
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/* Window x - size - 256 MB */
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reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), size);
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}
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mv_xor_hal_init(0);
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return;
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}
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static void mv_xor_finish2(void)
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{
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reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN),
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xor_ctrl_save);
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reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
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xor_base_save);
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reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
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xor_mask_save);
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}
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static void dram_ecc_scrubbing(void)
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{
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int cs;
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u32 size, temp;
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u32 total_mem = 0;
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u64 total;
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u32 start_addr;
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/*
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* The DDR training code from the bin_hdr / SPL already
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* scrubbed the DDR till 0x1000000. And the main U-Boot
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* is loaded to an address < 0x1000000. So we need to
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* skip this range to not re-scrub this area again.
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*/
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temp = reg_read(REG_SDRAM_CONFIG_ADDR);
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temp |= (1 << REG_SDRAM_CONFIG_IERR_OFFS);
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reg_write(REG_SDRAM_CONFIG_ADDR, temp);
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for (cs = 0; cs < CONFIG_NR_DRAM_BANKS; cs++) {
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size = mvebu_sdram_bs(cs);
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if (size == 0)
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continue;
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total = (u64)size;
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total_mem += (u32)(total / (1 << 30));
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start_addr = 0;
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mv_xor_init2(cs);
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/* Skip first 16 MiB */
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if (0 == cs) {
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start_addr = 0x1000000;
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size -= start_addr;
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}
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mv_xor_mem_init(SCRB_XOR_CHAN, start_addr, size - 1,
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SCRUB_MAGIC, SCRUB_MAGIC);
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/* Wait for previous transfer completion */
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while (mv_xor_state_get(SCRB_XOR_CHAN) != MV_IDLE)
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;
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mv_xor_finish2();
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}
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temp = reg_read(REG_SDRAM_CONFIG_ADDR);
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temp &= ~(1 << REG_SDRAM_CONFIG_IERR_OFFS);
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reg_write(REG_SDRAM_CONFIG_ADDR, temp);
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}
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static int ecc_enabled(void)
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{
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if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS))
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return 1;
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return 0;
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}
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/* Return the width of the DRAM bus, or 0 for unknown. */
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static int bus_width(void)
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{
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int full_width = 0;
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if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS))
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full_width = 1;
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switch (mvebu_soc_family()) {
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case MVEBU_SOC_AXP:
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return full_width ? 64 : 32;
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break;
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case MVEBU_SOC_A375:
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case MVEBU_SOC_A38X:
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case MVEBU_SOC_MSYS:
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return full_width ? 32 : 16;
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default:
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return 0;
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}
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}
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static int cycle_mode(void)
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{
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int val = reg_read(REG_DUNIT_CTRL_LOW_ADDR);
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return (val >> REG_DUNIT_CTRL_LOW_2T_OFFS) & REG_DUNIT_CTRL_LOW_2T_MASK;
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}
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#else
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static void dram_ecc_scrubbing(void)
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{
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}
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static int ecc_enabled(void)
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{
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return 0;
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}
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#endif
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int dram_init(void)
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{
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u64 size = 0;
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int i;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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/*
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* It is assumed that all memory banks are consecutive
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* and without gaps.
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* If the gap is found, ram_size will be reported for
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* consecutive memory only
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*/
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if (mvebu_sdram_bar(i) != size)
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break;
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/*
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* Don't report more than 3GiB of SDRAM, otherwise there is no
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* address space left for the internal registers etc.
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*/
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size += mvebu_sdram_bs(i);
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if (size > MVEBU_SDRAM_SIZE_MAX)
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size = MVEBU_SDRAM_SIZE_MAX;
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}
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if (ecc_enabled())
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dram_ecc_scrubbing();
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gd->ram_size = size;
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return 0;
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}
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/*
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* If this function is not defined here,
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* board.c alters dram bank zero configuration defined above.
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*/
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int dram_init_banksize(void)
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{
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u64 size = 0;
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int i;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
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gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
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/* Clip the banksize to 1GiB if it exceeds the max size */
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size += gd->bd->bi_dram[i].size;
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if (size > MVEBU_SDRAM_SIZE_MAX)
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mvebu_sdram_bs_set(i, 0x40000000);
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}
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return 0;
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}
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#if defined(CONFIG_ARCH_MVEBU)
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void board_add_ram_info(int use_default)
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{
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struct sar_freq_modes sar_freq;
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int mode;
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int width;
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get_sar_freq(&sar_freq);
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printf(" (%d MHz, ", sar_freq.d_clk);
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width = bus_width();
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if (width)
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printf("%d-bit, ", width);
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mode = cycle_mode();
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/* Mode 0 = Single cycle
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* Mode 1 = Two cycles (2T)
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* Mode 2 = Three cycles (3T)
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*/
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if (mode == 1)
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printf("2T, ");
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if (mode == 2)
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printf("3T, ");
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if (ecc_enabled())
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printf("ECC");
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else
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printf("ECC not");
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printf(" enabled)");
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}
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#endif
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