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982fab393d
The rk3308 only support RMII mode, and if it is output clock mode, better to use ref_clk pin with drive strength 12ma. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
1851 lines
41 KiB
Text
1851 lines
41 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
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*
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*/
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#include <dt-bindings/clock/rk3308-cru.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "rockchip,rk3308";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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spi0 = &spi0;
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spi1 = &spi1;
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spi2 = &spi2;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35", "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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clocks = <&cru ARMCLK>;
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#cooling-cells = <2>;
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dynamic-power-coefficient = <90>;
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operating-points-v2 = <&cpu0_opp_table>;
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cpu-idle-states = <&CPU_SLEEP>;
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35", "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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cpu-idle-states = <&CPU_SLEEP>;
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a35", "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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cpu-idle-states = <&CPU_SLEEP>;
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a35", "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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cpu-idle-states = <&CPU_SLEEP>;
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next-level-cache = <&l2>;
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};
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idle-states {
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entry-method = "psci";
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CPU_SLEEP: cpu-sleep {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <120>;
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exit-latency-us = <250>;
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min-residency-us = <900>;
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};
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};
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l2: l2-cache {
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compatible = "cache";
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};
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};
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cpu0_opp_table: cpu0-opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <950000 950000 1340000>;
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clock-latency-ns = <40000>;
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opp-suspend;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <950000 950000 1340000>;
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clock-latency-ns = <40000>;
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <1025000 1025000 1340000>;
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clock-latency-ns = <40000>;
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1125000 1125000 1340000>;
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clock-latency-ns = <40000>;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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mac_clkin: external-mac-clock {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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clock-output-names = "mac_clkin";
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#clock-cells = <0>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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xin24m: xin24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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};
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grf: grf@ff000000 {
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compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
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reg = <0x0 0xff000000 0x0 0x10000>;
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};
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dmc: dmc@0xff010000 {
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compatible = "rockchip,rk3308-dmc";
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reg = <0x0 0xff010000 0x0 0x10000>;
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};
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detect_grf: syscon@ff00b000 {
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compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
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reg = <0x0 0xff00b000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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core_grf: syscon@ff00c000 {
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compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
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reg = <0x0 0xff00c000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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i2c0: i2c@ff040000 {
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compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
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reg = <0x0 0xff040000 0x0 0x1000>;
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clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
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clock-names = "i2c", "pclk";
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_xfer>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@ff050000 {
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compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
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reg = <0x0 0xff050000 0x0 0x1000>;
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clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
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clock-names = "i2c", "pclk";
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_xfer>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@ff060000 {
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compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
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reg = <0x0 0xff060000 0x0 0x1000>;
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clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
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clock-names = "i2c", "pclk";
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_xfer>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@ff070000 {
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compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
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reg = <0x0 0xff070000 0x0 0x1000>;
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clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
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clock-names = "i2c", "pclk";
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3m0_xfer>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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wdt: watchdog@ff080000 {
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compatible = "snps,dw-wdt";
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reg = <0x0 0xff080000 0x0 0x100>;
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clocks = <&cru PCLK_WDT>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart0: serial@ff0a0000 {
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compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff0a0000 0x0 0x100>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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status = "disabled";
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};
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uart1: serial@ff0b0000 {
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compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff0b0000 0x0 0x100>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
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status = "disabled";
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};
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uart2: serial@ff0c0000 {
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compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff0c0000 0x0 0x100>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m0_xfer>;
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status = "disabled";
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};
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uart3: serial@ff0d0000 {
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compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff0d0000 0x0 0x100>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_xfer>;
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status = "disabled";
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};
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uart4: serial@ff0e0000 {
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compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff0e0000 0x0 0x100>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
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status = "disabled";
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};
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spi0: spi@ff120000 {
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compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff120000 0x0 0x1000>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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clock-names = "spiclk", "apb_pclk";
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dmas = <&dmac0 0>, <&dmac0 1>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "high_speed";
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pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
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pinctrl-1 = <&spi0_clk_hs &spi0_csn0 &spi0_miso_hs &spi0_mosi_hs>;
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status = "disabled";
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};
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spi1: spi@ff130000 {
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compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff130000 0x0 0x1000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
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clock-names = "spiclk", "apb_pclk";
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dmas = <&dmac0 2>, <&dmac0 3>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "high_speed";
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pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
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pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_miso_hs &spi1_mosi_hs>;
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status = "disabled";
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};
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spi2: spi@ff140000 {
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compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff140000 0x0 0x1000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
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clock-names = "spiclk", "apb_pclk";
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dmas = <&dmac1 16>, <&dmac1 17>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "high_speed";
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pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
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pinctrl-1 = <&spi2_clk_hs &spi2_csn0 &spi2_miso_hs &spi2_mosi_hs>;
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status = "disabled";
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};
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pwm8: pwm@ff160000 {
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compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
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reg = <0x0 0xff160000 0x0 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm8_pin>;
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clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
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clock-names = "pwm", "pclk";
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status = "disabled";
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};
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pwm9: pwm@ff160010 {
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compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
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reg = <0x0 0xff160010 0x0 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm9_pin>;
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clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
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clock-names = "pwm", "pclk";
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status = "disabled";
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};
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pwm10: pwm@ff160020 {
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compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
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reg = <0x0 0xff160020 0x0 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm10_pin>;
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clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
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clock-names = "pwm", "pclk";
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status = "disabled";
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};
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pwm11: pwm@ff160030 {
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compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
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reg = <0x0 0xff160030 0x0 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm11_pin>;
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clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
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clock-names = "pwm", "pclk";
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status = "disabled";
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};
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pwm4: pwm@ff170000 {
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compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
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reg = <0x0 0xff170000 0x0 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm4_pin>;
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clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
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clock-names = "pwm", "pclk";
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status = "disabled";
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};
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pwm5: pwm@ff170010 {
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compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
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reg = <0x0 0xff170010 0x0 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm5_pin>;
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clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
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clock-names = "pwm", "pclk";
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status = "disabled";
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};
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pwm6: pwm@ff170020 {
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compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
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reg = <0x0 0xff170020 0x0 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm6_pin>;
|
|
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm7: pwm@ff170030 {
|
|
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xff170030 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm7_pin>;
|
|
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@ff180000 {
|
|
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xff180000 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm0_pin>;
|
|
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@ff180010 {
|
|
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xff180010 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm1_pin>;
|
|
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@ff180020 {
|
|
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xff180020 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm2_pin>;
|
|
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@ff180030 {
|
|
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xff180030 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm3_pin>;
|
|
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
rktimer: rktimer@ff1a0000 {
|
|
compatible = "rockchip,rk3288-timer";
|
|
reg = <0x0 0xff1a0000 0x0 0x20>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
|
|
clock-names = "pclk", "timer";
|
|
};
|
|
|
|
saradc: saradc@ff1e0000 {
|
|
compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
|
|
reg = <0x0 0xff1e0000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
#io-channel-cells = <1>;
|
|
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
|
|
clock-names = "saradc", "apb_pclk";
|
|
resets = <&cru SRST_SARADC_P>;
|
|
reset-names = "saradc-apb";
|
|
status = "disabled";
|
|
};
|
|
|
|
amba {
|
|
compatible = "arm,amba-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
dmac0: dma-controller@ff2c0000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x0 0xff2c0000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
clocks = <&cru ACLK_DMAC0>;
|
|
clock-names = "apb_pclk";
|
|
peripherals-req-type-burst;
|
|
};
|
|
|
|
dmac1: dma-controller@ff2d0000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x0 0xff2d0000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
clocks = <&cru ACLK_DMAC1>;
|
|
clock-names = "apb_pclk";
|
|
peripherals-req-type-burst;
|
|
};
|
|
};
|
|
|
|
i2s_2ch_0: i2s@ff350000 {
|
|
compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
|
|
reg = <0x0 0xff350000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>;
|
|
clock-names = "i2s_clk", "i2s_hclk";
|
|
dmas = <&dmac1 8>, <&dmac1 9>;
|
|
dma-names = "tx", "rx";
|
|
resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>;
|
|
reset-names = "reset-m", "reset-h";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s_2ch_0_sclk
|
|
&i2s_2ch_0_lrck
|
|
&i2s_2ch_0_sdi
|
|
&i2s_2ch_0_sdo>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s_2ch_1: i2s@ff360000 {
|
|
compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
|
|
reg = <0x0 0xff360000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>;
|
|
clock-names = "i2s_clk", "i2s_hclk";
|
|
dmas = <&dmac1 11>;
|
|
dma-names = "rx";
|
|
resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>;
|
|
reset-names = "reset-m", "reset-h";
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif_tx: spdif-tx@ff3a0000 {
|
|
compatible = "rockchip,rk3308-spdif", "rockchip,rk3328-spdif";
|
|
reg = <0x0 0xff3a0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
|
|
clock-names = "mclk", "hclk";
|
|
dmas = <&dmac1 13>;
|
|
dma-names = "tx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spdif_out>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdmmc: dwmmc@ff480000 {
|
|
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
reg = <0x0 0xff480000 0x0 0x4000>;
|
|
max-frequency = <150000000>;
|
|
bus-width = <4>;
|
|
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
|
|
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
|
|
clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
emmc: dwmmc@ff490000 {
|
|
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
reg = <0x0 0xff490000 0x0 0x4000>;
|
|
max-frequency = <150000000>;
|
|
bus-width = <8>;
|
|
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
|
|
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
|
|
clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdio: dwmmc@ff4a0000 {
|
|
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
reg = <0x0 0xff4a0000 0x0 0x4000>;
|
|
max-frequency = <150000000>;
|
|
bus-width = <4>;
|
|
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
|
|
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
|
|
clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mac: ethernet@ff4e0000 {
|
|
compatible = "rockchip,rk3308-mac";
|
|
reg = <0x0 0xff4e0000 0x0 0x10000>;
|
|
rockchip,grf = <&grf>;
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
|
|
<&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
|
|
<&cru SCLK_MAC>, <&cru ACLK_MAC>,
|
|
<&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
|
|
clock-names = "stmmaceth", "mac_clk_rx",
|
|
"mac_clk_tx", "clk_mac_ref",
|
|
"clk_mac_refout", "aclk_mac",
|
|
"pclk_mac", "clk_mac_speed";
|
|
phy-mode = "rmii";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
|
|
resets = <&cru SRST_MAC_A>;
|
|
reset-names = "stmmaceth";
|
|
status = "disabled";
|
|
};
|
|
|
|
cru: clock-controller@ff500000 {
|
|
compatible = "rockchip,rk3308-cru";
|
|
reg = <0x0 0xff500000 0x0 0x1000>;
|
|
rockchip,grf = <&grf>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gic: interrupt-controller@ff580000 {
|
|
compatible = "arm,gic-400";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
|
|
reg = <0x0 0xff581000 0x0 0x1000>,
|
|
<0x0 0xff582000 0x0 0x2000>,
|
|
<0x0 0xff584000 0x0 0x2000>,
|
|
<0x0 0xff586000 0x0 0x2000>;
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sram: sram@fff80000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x0 0xfff80000 0x0 0x40000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x0 0xfff80000 0x40000>;
|
|
/* reserved for ddr dvfs and system suspend/resume */
|
|
ddr-sram@0 {
|
|
reg = <0x0 0x8000>;
|
|
};
|
|
/* reserved for vad audio buffer */
|
|
vad_sram: vad-sram@8000 {
|
|
reg = <0x8000 0x38000>;
|
|
};
|
|
};
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "rockchip,rk3308-pinctrl";
|
|
rockchip,grf = <&grf>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
gpio0: gpio0@ff220000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff220000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO0>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio1: gpio1@ff230000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff230000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO1>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio2@ff240000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff240000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO2>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio3@ff250000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff250000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO3>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio4: gpio4@ff260000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff260000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
pcfg_pull_up: pcfg-pull-up {
|
|
bias-pull-up;
|
|
};
|
|
|
|
pcfg_pull_down: pcfg-pull-down {
|
|
bias-pull-down;
|
|
};
|
|
|
|
pcfg_pull_none: pcfg-pull-none {
|
|
bias-disable;
|
|
};
|
|
|
|
pcfg_pull_none_2ma: pcfg-pull-none-2ma {
|
|
bias-disable;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
pcfg_pull_up_2ma: pcfg-pull-up-2ma {
|
|
bias-pull-up;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
pcfg_pull_up_4ma: pcfg-pull-up-4ma {
|
|
bias-pull-up;
|
|
drive-strength = <4>;
|
|
};
|
|
|
|
pcfg_pull_none_4ma: pcfg-pull-none-4ma {
|
|
bias-disable;
|
|
drive-strength = <4>;
|
|
};
|
|
|
|
pcfg_pull_down_4ma: pcfg-pull-down-4ma {
|
|
bias-pull-down;
|
|
drive-strength = <4>;
|
|
};
|
|
|
|
pcfg_pull_none_8ma: pcfg-pull-none-8ma {
|
|
bias-disable;
|
|
drive-strength = <8>;
|
|
};
|
|
|
|
pcfg_pull_up_8ma: pcfg-pull-up-8ma {
|
|
bias-pull-up;
|
|
drive-strength = <8>;
|
|
};
|
|
|
|
pcfg_pull_none_12ma: pcfg-pull-none-12ma {
|
|
bias-disable;
|
|
drive-strength = <12>;
|
|
};
|
|
|
|
pcfg_pull_up_12ma: pcfg-pull-up-12ma {
|
|
bias-pull-up;
|
|
drive-strength = <12>;
|
|
};
|
|
|
|
pcfg_pull_none_smt: pcfg-pull-none-smt {
|
|
bias-disable;
|
|
input-schmitt-enable;
|
|
};
|
|
|
|
pcfg_output_high: pcfg-output-high {
|
|
output-high;
|
|
};
|
|
|
|
pcfg_output_low: pcfg-output-low {
|
|
output-low;
|
|
};
|
|
|
|
pcfg_input_high: pcfg-input-high {
|
|
bias-pull-up;
|
|
input-enable;
|
|
};
|
|
|
|
pcfg_input: pcfg-input {
|
|
input-enable;
|
|
};
|
|
|
|
i2c0 {
|
|
i2c0_xfer: i2c0-xfer {
|
|
rockchip,pins =
|
|
<1 RK_PD0 2 &pcfg_pull_none_smt>,
|
|
<1 RK_PD1 2 &pcfg_pull_none_smt>;
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
i2c1_xfer: i2c1-xfer {
|
|
rockchip,pins =
|
|
<0 RK_PB3 1 &pcfg_pull_none_smt>,
|
|
<0 RK_PB4 1 &pcfg_pull_none_smt>;
|
|
};
|
|
};
|
|
|
|
i2c2 {
|
|
i2c2_xfer: i2c2-xfer {
|
|
rockchip,pins =
|
|
<2 RK_PA2 3 &pcfg_pull_none_smt>,
|
|
<2 RK_PA3 3 &pcfg_pull_none_smt>;
|
|
};
|
|
};
|
|
|
|
i2c3-m0 {
|
|
i2c3m0_xfer: i2c3m0-xfer {
|
|
rockchip,pins =
|
|
<0 RK_PB7 2 &pcfg_pull_none_smt>,
|
|
<0 RK_PC0 2 &pcfg_pull_none_smt>;
|
|
};
|
|
};
|
|
|
|
i2c3-m1 {
|
|
i2c3m1_xfer: i2c3m1-xfer {
|
|
rockchip,pins =
|
|
<3 RK_PB4 2 &pcfg_pull_none_smt>,
|
|
<3 RK_PB5 2 &pcfg_pull_none_smt>;
|
|
};
|
|
};
|
|
|
|
i2c3-m2 {
|
|
i2c3m2_xfer: i2c3m2-xfer {
|
|
rockchip,pins =
|
|
<2 RK_PA1 3 &pcfg_pull_none_smt>,
|
|
<2 RK_PA0 3 &pcfg_pull_none_smt>;
|
|
};
|
|
};
|
|
|
|
i2s_2ch_0 {
|
|
i2s_2ch_0_mclk: i2s-2ch-0-mclk {
|
|
rockchip,pins =
|
|
<4 RK_PB4 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_2ch_0_sclk: i2s-2ch-0-sclk {
|
|
rockchip,pins =
|
|
<4 RK_PB5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_2ch_0_lrck: i2s-2ch-0-lrck {
|
|
rockchip,pins =
|
|
<4 RK_PB6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_2ch_0_sdo: i2s-2ch-0-sdo {
|
|
rockchip,pins =
|
|
<4 RK_PB7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_2ch_0_sdi: i2s-2ch-0-sdi {
|
|
rockchip,pins =
|
|
<4 RK_PC0 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2s_8ch_0 {
|
|
i2s_8ch_0_mclk: i2s-8ch-0-mclk {
|
|
rockchip,pins =
|
|
<2 RK_PA4 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
|
|
rockchip,pins =
|
|
<2 RK_PA5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
|
|
rockchip,pins =
|
|
<2 RK_PA6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
|
|
rockchip,pins =
|
|
<2 RK_PA7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
|
|
rockchip,pins =
|
|
<2 RK_PB0 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
|
|
rockchip,pins =
|
|
<2 RK_PB1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
|
|
rockchip,pins =
|
|
<2 RK_PB2 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
|
|
rockchip,pins =
|
|
<2 RK_PB3 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
|
|
rockchip,pins =
|
|
<2 RK_PB4 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
|
|
rockchip,pins =
|
|
<2 RK_PB5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
|
|
rockchip,pins =
|
|
<2 RK_PB6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
|
|
rockchip,pins =
|
|
<2 RK_PB7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
|
|
rockchip,pins =
|
|
<2 RK_PC0 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2s_8ch_1_m0 {
|
|
i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
|
|
rockchip,pins =
|
|
<1 RK_PA2 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
|
|
rockchip,pins =
|
|
<1 RK_PA3 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
|
|
rockchip,pins =
|
|
<1 RK_PA4 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
|
|
rockchip,pins =
|
|
<1 RK_PA5 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
|
|
rockchip,pins =
|
|
<1 RK_PA6 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
|
|
rockchip,pins =
|
|
<1 RK_PA7 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
|
|
rockchip,pins =
|
|
<1 RK_PB0 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
|
|
rockchip,pins =
|
|
<1 RK_PB1 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
|
|
rockchip,pins =
|
|
<1 RK_PB2 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
|
|
rockchip,pins =
|
|
<1 RK_PB3 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2s_8ch_1_m1 {
|
|
i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
|
|
rockchip,pins =
|
|
<1 RK_PB4 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
|
|
rockchip,pins =
|
|
<1 RK_PB5 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
|
|
rockchip,pins =
|
|
<1 RK_PB6 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
|
|
rockchip,pins =
|
|
<1 RK_PB7 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
|
|
rockchip,pins =
|
|
<1 RK_PC0 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
|
|
rockchip,pins =
|
|
<1 RK_PC1 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
|
|
rockchip,pins =
|
|
<1 RK_PC2 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
|
|
rockchip,pins =
|
|
<1 RK_PC3 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
|
|
rockchip,pins =
|
|
<1 RK_PC4 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
|
|
rockchip,pins =
|
|
<1 RK_PC5 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pdm_m0 {
|
|
pdm_m0_clk: pdm-m0-clk {
|
|
rockchip,pins =
|
|
<1 RK_PA4 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdm_m0_sdi0: pdm-m0-sdi0 {
|
|
rockchip,pins =
|
|
<1 RK_PB3 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdm_m0_sdi1: pdm-m0-sdi1 {
|
|
rockchip,pins =
|
|
<1 RK_PB2 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdm_m0_sdi2: pdm-m0-sdi2 {
|
|
rockchip,pins =
|
|
<1 RK_PB1 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdm_m0_sdi3: pdm-m0-sdi3 {
|
|
rockchip,pins =
|
|
<1 RK_PB0 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pdm_m1 {
|
|
pdm_m1_clk: pdm-m1-clk {
|
|
rockchip,pins =
|
|
<1 RK_PB6 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdm_m1_sdi0: pdm-m1-sdi0 {
|
|
rockchip,pins =
|
|
<1 RK_PC5 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdm_m1_sdi1: pdm-m1-sdi1 {
|
|
rockchip,pins =
|
|
<1 RK_PC4 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdm_m1_sdi2: pdm-m1-sdi2 {
|
|
rockchip,pins =
|
|
<1 RK_PC3 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdm_m1_sdi3: pdm-m1-sdi3 {
|
|
rockchip,pins =
|
|
<1 RK_PC2 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pdm_m2 {
|
|
pdm_m2_clkm: pdm-m2-clkm {
|
|
rockchip,pins =
|
|
<2 RK_PA4 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdm_m2_clk: pdm-m2-clk {
|
|
rockchip,pins =
|
|
<2 RK_PA6 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdm_m2_sdi0: pdm-m2-sdi0 {
|
|
rockchip,pins =
|
|
<2 RK_PB5 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdm_m2_sdi1: pdm-m2-sdi1 {
|
|
rockchip,pins =
|
|
<2 RK_PB6 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdm_m2_sdi2: pdm-m2-sdi2 {
|
|
rockchip,pins =
|
|
<2 RK_PB7 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdm_m2_sdi3: pdm-m2-sdi3 {
|
|
rockchip,pins =
|
|
<2 RK_PC0 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spdif_in {
|
|
spdif_in: spdif-in {
|
|
rockchip,pins =
|
|
<0 RK_PC2 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spdif_out {
|
|
spdif_out: spdif-out {
|
|
rockchip,pins =
|
|
<0 RK_PC1 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
tsadc {
|
|
tsadc_otp_gpio: tsadc-otp-gpio {
|
|
rockchip,pins =
|
|
<0 RK_PB2 0 &pcfg_pull_none>;
|
|
};
|
|
|
|
tsadc_otp_out: tsadc-otp-out {
|
|
rockchip,pins =
|
|
<0 RK_PB2 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
uart0_xfer: uart0-xfer {
|
|
rockchip,pins =
|
|
<2 RK_PA1 1 &pcfg_pull_up>,
|
|
<2 RK_PA0 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart0_cts: uart0-cts {
|
|
rockchip,pins =
|
|
<2 RK_PA2 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_rts: uart0-rts {
|
|
rockchip,pins =
|
|
<2 RK_PA3 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_rts_gpio: uart0-rts-gpio {
|
|
rockchip,pins =
|
|
<2 RK_PA3 0 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
uart1_xfer: uart1-xfer {
|
|
rockchip,pins =
|
|
<1 RK_PD1 1 &pcfg_pull_up>,
|
|
<1 RK_PD0 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart1_cts: uart1-cts {
|
|
rockchip,pins =
|
|
<1 RK_PC6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_rts: uart1-rts {
|
|
rockchip,pins =
|
|
<1 RK_PC7 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2-m0 {
|
|
uart2m0_xfer: uart2m0-xfer {
|
|
rockchip,pins =
|
|
<1 RK_PC7 2 &pcfg_pull_up>,
|
|
<1 RK_PC6 2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
uart2-m1 {
|
|
uart2m1_xfer: uart2m1-xfer {
|
|
rockchip,pins =
|
|
<4 RK_PD3 2 &pcfg_pull_up>,
|
|
<4 RK_PD2 2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
uart3 {
|
|
uart3_xfer: uart3-xfer {
|
|
rockchip,pins =
|
|
<3 RK_PB5 4 &pcfg_pull_up>,
|
|
<3 RK_PB4 4 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
uart3-m1 {
|
|
uart3m1_xfer: uart3m1-xfer {
|
|
rockchip,pins =
|
|
<0 RK_PC2 3 &pcfg_pull_up>,
|
|
<0 RK_PC1 3 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
uart4 {
|
|
|
|
uart4_xfer: uart4-xfer {
|
|
rockchip,pins =
|
|
<4 RK_PB1 1 &pcfg_pull_up>,
|
|
<4 RK_PB0 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart4_cts: uart4-cts {
|
|
rockchip,pins =
|
|
<4 RK_PA6 1 &pcfg_pull_none>;
|
|
|
|
};
|
|
|
|
uart4_rts: uart4-rts {
|
|
rockchip,pins =
|
|
<4 RK_PA7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart4_rts_gpio: uart4-rts-gpio {
|
|
rockchip,pins =
|
|
<4 RK_PA7 0 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
spi0_clk: spi0-clk {
|
|
rockchip,pins =
|
|
<2 RK_PA2 2 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
spi0_csn0: spi0-csn0 {
|
|
rockchip,pins =
|
|
<2 RK_PA3 2 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
spi0_miso: spi0-miso {
|
|
rockchip,pins =
|
|
<2 RK_PA0 2 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
spi0_mosi: spi0-mosi {
|
|
rockchip,pins =
|
|
<2 RK_PA1 2 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
spi0_clk_hs: spi0-clk-hs {
|
|
rockchip,pins =
|
|
<2 RK_PA2 2 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
spi0_miso_hs: spi0-miso-hs {
|
|
rockchip,pins =
|
|
<2 RK_PA0 2 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
spi0_mosi_hs: spi0-mosi-hs {
|
|
rockchip,pins =
|
|
<2 RK_PA1 2 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
};
|
|
|
|
spi1 {
|
|
spi1_clk: spi1-clk {
|
|
rockchip,pins =
|
|
<3 RK_PB3 3 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
spi1_csn0: spi1-csn0 {
|
|
rockchip,pins =
|
|
<3 RK_PB5 3 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
spi1_miso: spi1-miso {
|
|
rockchip,pins =
|
|
<3 RK_PB2 3 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
spi1_mosi: spi1-mosi {
|
|
rockchip,pins =
|
|
<3 RK_PB4 3 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
spi1_clk_hs: spi1-clk-hs {
|
|
rockchip,pins =
|
|
<3 RK_PB3 3 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
spi1_miso_hs: spi1-miso-hs {
|
|
rockchip,pins =
|
|
<3 RK_PB2 3 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
spi1_mosi_hs: spi1-mosi-hs {
|
|
rockchip,pins =
|
|
<3 RK_PB4 3 &pcfg_pull_up_8ma>;
|
|
};
|
|
};
|
|
|
|
spi1-m1 {
|
|
spi1m1_miso: spi1m1-miso {
|
|
rockchip,pins =
|
|
<2 RK_PA4 2 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
spi1m1_mosi: spi1m1-mosi {
|
|
rockchip,pins =
|
|
<2 RK_PA5 2 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
spi1m1_clk: spi1m1-clk {
|
|
rockchip,pins =
|
|
<2 RK_PA7 2 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
spi1m1_csn0: spi1m1-csn0 {
|
|
rockchip,pins =
|
|
<2 RK_PB1 2 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
spi1m1_miso_hs: spi1m1-miso-hs {
|
|
rockchip,pins =
|
|
<2 RK_PA4 2 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
spi1m1_mosi_hs: spi1m1-mosi-hs {
|
|
rockchip,pins =
|
|
<2 RK_PA5 2 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
spi1m1_clk_hs: spi1m1-clk-hs {
|
|
rockchip,pins =
|
|
<2 RK_PA7 2 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
spi1m1_csn0_hs: spi1m1-csn0-hs {
|
|
rockchip,pins =
|
|
<2 RK_PB1 2 &pcfg_pull_up_8ma>;
|
|
};
|
|
};
|
|
|
|
spi2 {
|
|
spi2_clk: spi2-clk {
|
|
rockchip,pins =
|
|
<1 RK_PD0 3 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
spi2_csn0: spi2-csn0 {
|
|
rockchip,pins =
|
|
<1 RK_PD1 3 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
spi2_miso: spi2-miso {
|
|
rockchip,pins =
|
|
<1 RK_PC6 3 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
spi2_mosi: spi2-mosi {
|
|
rockchip,pins =
|
|
<1 RK_PC7 3 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
spi2_clk_hs: spi2-clk-hs {
|
|
rockchip,pins =
|
|
<1 RK_PD0 3 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
spi2_miso_hs: spi2-miso-hs {
|
|
rockchip,pins =
|
|
<1 RK_PC6 3 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
spi2_mosi_hs: spi2-mosi-hs {
|
|
rockchip,pins =
|
|
<1 RK_PC7 3 &pcfg_pull_up_8ma>;
|
|
};
|
|
};
|
|
|
|
sdmmc {
|
|
sdmmc_clk: sdmmc-clk {
|
|
rockchip,pins =
|
|
<4 RK_PD5 1 &pcfg_pull_none_4ma>;
|
|
};
|
|
|
|
sdmmc_cmd: sdmmc-cmd {
|
|
rockchip,pins =
|
|
<4 RK_PD4 1 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
sdmmc_det: sdmmc-det {
|
|
rockchip,pins =
|
|
<0 RK_PA3 1 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
sdmmc_pwren: sdmmc-pwren {
|
|
rockchip,pins =
|
|
<4 RK_PD6 1 &pcfg_pull_none_4ma>;
|
|
};
|
|
|
|
sdmmc_bus1: sdmmc-bus1 {
|
|
rockchip,pins =
|
|
<4 RK_PD0 1 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
sdmmc_bus4: sdmmc-bus4 {
|
|
rockchip,pins =
|
|
<4 RK_PD0 1 &pcfg_pull_up_4ma>,
|
|
<4 RK_PD1 1 &pcfg_pull_up_4ma>,
|
|
<4 RK_PD2 1 &pcfg_pull_up_4ma>,
|
|
<4 RK_PD3 1 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
sdmmc_gpio: sdmmc-gpio {
|
|
rockchip,pins =
|
|
<4 RK_PD0 0 &pcfg_pull_up_4ma>,
|
|
<4 RK_PD1 0 &pcfg_pull_up_4ma>,
|
|
<4 RK_PD2 0 &pcfg_pull_up_4ma>,
|
|
<4 RK_PD3 0 &pcfg_pull_up_4ma>,
|
|
<4 RK_PD4 0 &pcfg_pull_up_4ma>,
|
|
<4 RK_PD5 0 &pcfg_pull_up_4ma>,
|
|
<4 RK_PD6 0 &pcfg_pull_up_4ma>;
|
|
};
|
|
};
|
|
|
|
sdio {
|
|
sdio_clk: sdio-clk {
|
|
rockchip,pins =
|
|
<4 RK_PA5 1 &pcfg_pull_none_8ma>;
|
|
};
|
|
|
|
sdio_cmd: sdio-cmd {
|
|
rockchip,pins =
|
|
<4 RK_PA4 1 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
sdio_pwren: sdio-pwren {
|
|
rockchip,pins =
|
|
<0 RK_PA2 1 &pcfg_pull_none_8ma>;
|
|
};
|
|
|
|
sdio_wrpt: sdio-wrpt {
|
|
rockchip,pins =
|
|
<0 RK_PA1 1 &pcfg_pull_none_8ma>;
|
|
};
|
|
|
|
sdio_intn: sdio-intn {
|
|
rockchip,pins =
|
|
<0 RK_PA0 1 &pcfg_pull_none_8ma>;
|
|
};
|
|
|
|
sdio_bus1: sdio-bus1 {
|
|
rockchip,pins =
|
|
<4 RK_PA0 1 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
sdio_bus4: sdio-bus4 {
|
|
rockchip,pins =
|
|
<4 RK_PA0 1 &pcfg_pull_up_8ma>,
|
|
<4 RK_PA1 1 &pcfg_pull_up_8ma>,
|
|
<4 RK_PA2 1 &pcfg_pull_up_8ma>,
|
|
<4 RK_PA3 1 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
sdio_gpio: sdio-gpio {
|
|
rockchip,pins =
|
|
<4 RK_PA0 0 &pcfg_pull_up_4ma>,
|
|
<4 RK_PA1 0 &pcfg_pull_up_4ma>,
|
|
<4 RK_PA2 0 &pcfg_pull_up_4ma>,
|
|
<4 RK_PA3 0 &pcfg_pull_up_4ma>,
|
|
<4 RK_PA4 0 &pcfg_pull_up_4ma>,
|
|
<4 RK_PA5 0 &pcfg_pull_up_4ma>;
|
|
};
|
|
};
|
|
|
|
emmc {
|
|
emmc_clk: emmc-clk {
|
|
rockchip,pins =
|
|
<3 RK_PB1 2 &pcfg_pull_none_8ma>;
|
|
};
|
|
|
|
emmc_cmd: emmc-cmd {
|
|
rockchip,pins =
|
|
<3 RK_PB0 2 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
emmc_pwren: emmc-pwren {
|
|
rockchip,pins =
|
|
<3 RK_PB3 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
emmc_rstn: emmc-rstn {
|
|
rockchip,pins =
|
|
<3 RK_PB2 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
emmc_bus1: emmc-bus1 {
|
|
rockchip,pins =
|
|
<3 RK_PA0 2 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
emmc_bus4: emmc-bus4 {
|
|
rockchip,pins =
|
|
<3 RK_PA0 2 &pcfg_pull_up_8ma>,
|
|
<3 RK_PA1 2 &pcfg_pull_up_8ma>,
|
|
<3 RK_PA2 2 &pcfg_pull_up_8ma>,
|
|
<3 RK_PA3 2 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
emmc_bus8: emmc-bus8 {
|
|
rockchip,pins =
|
|
<3 RK_PA0 2 &pcfg_pull_up_8ma>,
|
|
<3 RK_PA1 2 &pcfg_pull_up_8ma>,
|
|
<3 RK_PA2 2 &pcfg_pull_up_8ma>,
|
|
<3 RK_PA3 2 &pcfg_pull_up_8ma>,
|
|
<3 RK_PA4 2 &pcfg_pull_up_8ma>,
|
|
<3 RK_PA5 2 &pcfg_pull_up_8ma>,
|
|
<3 RK_PA6 2 &pcfg_pull_up_8ma>,
|
|
<3 RK_PA7 2 &pcfg_pull_up_8ma>;
|
|
};
|
|
};
|
|
|
|
flash {
|
|
flash_csn0: flash-csn0 {
|
|
rockchip,pins =
|
|
<3 RK_PB5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
flash_rdy: flash-rdy {
|
|
rockchip,pins =
|
|
<3 RK_PB4 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
flash_ale: flash-ale {
|
|
rockchip,pins =
|
|
<3 RK_PB3 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
flash_cle: flash-cle {
|
|
rockchip,pins =
|
|
<3 RK_PB1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
flash_wrn: flash-wrn {
|
|
rockchip,pins =
|
|
<3 RK_PB0 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
flash_rdn: flash-rdn {
|
|
rockchip,pins =
|
|
<3 RK_PB2 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
flash_bus8: flash-bus8 {
|
|
rockchip,pins =
|
|
<3 RK_PA0 1 &pcfg_pull_up_12ma>,
|
|
<3 RK_PA1 1 &pcfg_pull_up_12ma>,
|
|
<3 RK_PA2 1 &pcfg_pull_up_12ma>,
|
|
<3 RK_PA3 1 &pcfg_pull_up_12ma>,
|
|
<3 RK_PA4 1 &pcfg_pull_up_12ma>,
|
|
<3 RK_PA5 1 &pcfg_pull_up_12ma>,
|
|
<3 RK_PA6 1 &pcfg_pull_up_12ma>,
|
|
<3 RK_PA7 1 &pcfg_pull_up_12ma>;
|
|
};
|
|
};
|
|
|
|
pwm0 {
|
|
pwm0_pin: pwm0-pin {
|
|
rockchip,pins =
|
|
<0 RK_PB5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm0_pin_pull_down: pwm0-pin-pull-down {
|
|
rockchip,pins =
|
|
<0 RK_PB5 1 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
pwm1 {
|
|
pwm1_pin: pwm1-pin {
|
|
rockchip,pins =
|
|
<0 RK_PB6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm1_pin_pull_down: pwm1-pin-pull-down {
|
|
rockchip,pins =
|
|
<0 RK_PB6 1 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
pwm2 {
|
|
pwm2_pin: pwm2-pin {
|
|
rockchip,pins =
|
|
<0 RK_PB7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm2_pin_pull_down: pwm2-pin-pull-down {
|
|
rockchip,pins =
|
|
<0 RK_PB7 1 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
pwm3 {
|
|
pwm3_pin: pwm3-pin {
|
|
rockchip,pins =
|
|
<0 RK_PC0 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm3_pin_pull_down: pwm3-pin-pull-down {
|
|
rockchip,pins =
|
|
<0 RK_PC0 1 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
pwm4 {
|
|
pwm4_pin: pwm4-pin {
|
|
rockchip,pins =
|
|
<0 RK_PA1 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm4_pin_pull_down: pwm4-pin-pull-down {
|
|
rockchip,pins =
|
|
<0 RK_PA1 2 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
pwm5 {
|
|
pwm5_pin: pwm5-pin {
|
|
rockchip,pins =
|
|
<0 RK_PC1 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm5_pin_pull_down: pwm5-pin-pull-down {
|
|
rockchip,pins =
|
|
<0 RK_PC1 2 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
pwm6 {
|
|
pwm6_pin: pwm6-pin {
|
|
rockchip,pins =
|
|
<0 RK_PC2 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm6_pin_pull_down: pwm6-pin-pull-down {
|
|
rockchip,pins =
|
|
<0 RK_PC2 2 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
pwm7 {
|
|
pwm7_pin: pwm7-pin {
|
|
rockchip,pins =
|
|
<2 RK_PB0 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm7_pin_pull_down: pwm7-pin-pull-down {
|
|
rockchip,pins =
|
|
<2 RK_PB0 2 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
pwm8 {
|
|
pwm8_pin: pwm8-pin {
|
|
rockchip,pins =
|
|
<2 RK_PB2 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm8_pin_pull_down: pwm8-pin-pull-down {
|
|
rockchip,pins =
|
|
<2 RK_PB2 2 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
pwm9 {
|
|
pwm9_pin: pwm9-pin {
|
|
rockchip,pins =
|
|
<2 RK_PB3 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm9_pin_pull_down: pwm9-pin-pull-down {
|
|
rockchip,pins =
|
|
<2 RK_PB3 2 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
pwm10 {
|
|
pwm10_pin: pwm10-pin {
|
|
rockchip,pins =
|
|
<2 RK_PB4 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm10_pin_pull_down: pwm10-pin-pull-down {
|
|
rockchip,pins =
|
|
<2 RK_PB4 2 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
pwm11 {
|
|
pwm11_pin: pwm11-pin {
|
|
rockchip,pins =
|
|
<2 RK_PC0 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm11_pin_pull_down: pwm11-pin-pull-down {
|
|
rockchip,pins =
|
|
<2 RK_PC0 4 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
gmac {
|
|
rmii_pins: rmii-pins {
|
|
rockchip,pins =
|
|
/* mac_txen */
|
|
<1 RK_PC1 3 &pcfg_pull_none_12ma>,
|
|
/* mac_txd1 */
|
|
<1 RK_PC3 3 &pcfg_pull_none_12ma>,
|
|
/* mac_txd0 */
|
|
<1 RK_PC2 3 &pcfg_pull_none_12ma>,
|
|
/* mac_rxd0 */
|
|
<1 RK_PC4 3 &pcfg_pull_none>,
|
|
/* mac_rxd1 */
|
|
<1 RK_PC5 3 &pcfg_pull_none>,
|
|
/* mac_rxer */
|
|
<1 RK_PB7 3 &pcfg_pull_none>,
|
|
/* mac_rxdv */
|
|
<1 RK_PC0 3 &pcfg_pull_none>,
|
|
/* mac_mdio */
|
|
<1 RK_PB6 3 &pcfg_pull_none>,
|
|
/* mac_mdc */
|
|
<1 RK_PB5 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
mac_refclk_12ma: mac-refclk-12ma {
|
|
rockchip,pins =
|
|
<1 RK_PB4 3 &pcfg_pull_none_12ma>;
|
|
};
|
|
|
|
mac_refclk: mac-refclk {
|
|
rockchip,pins =
|
|
<1 RK_PB4 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
gmac-m1 {
|
|
rmiim1_pins: rmiim1-pins {
|
|
rockchip,pins =
|
|
/* mac_txen */
|
|
<4 RK_PB7 2 &pcfg_pull_none_12ma>,
|
|
/* mac_txd1 */
|
|
<4 RK_PA5 2 &pcfg_pull_none_12ma>,
|
|
/* mac_txd0 */
|
|
<4 RK_PA4 2 &pcfg_pull_none_12ma>,
|
|
/* mac_rxd0 */
|
|
<4 RK_PA2 2 &pcfg_pull_none>,
|
|
/* mac_rxd1 */
|
|
<4 RK_PA3 2 &pcfg_pull_none>,
|
|
/* mac_rxer */
|
|
<4 RK_PA0 2 &pcfg_pull_none>,
|
|
/* mac_rxdv */
|
|
<4 RK_PA1 2 &pcfg_pull_none>,
|
|
/* mac_mdio */
|
|
<4 RK_PB6 2 &pcfg_pull_none>,
|
|
/* mac_mdc */
|
|
<4 RK_PB5 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
macm1_refclk_12ma: macm1-refclk-12ma {
|
|
rockchip,pins =
|
|
<4 RK_PB4 2 &pcfg_pull_none_12ma>;
|
|
};
|
|
|
|
macm1_refclk: macm1-refclk {
|
|
rockchip,pins =
|
|
<4 RK_PB4 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
rtc {
|
|
rtc_32k: rtc-32k {
|
|
rockchip,pins =
|
|
<0 RK_PC3 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|