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39dd4f628f
The eth aliases are for correct probing order, so that each Ethernet port will get a predictable MAC address from the environment. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
180 lines
2.8 KiB
Text
180 lines
2.8 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/* Copyright 2016-2018 NXP
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* Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
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*/
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/dts-v1/;
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#include "ls1021a.dtsi"
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/ {
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model = "NXP LS1021A-TSN Board";
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aliases {
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enet0-sgmii-phy = &sgmii_phy2;
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enet1-sgmii-phy = &sgmii_phy1;
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spi0 = &qspi;
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spi1 = &dspi1;
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &swp2;
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ethernet4 = &swp3;
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ethernet5 = &swp4;
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ethernet6 = &swp5;
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};
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};
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&dspi0 {
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bus-num = <0>;
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status = "okay";
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sja1105: ethernet-switch@1 {
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reg = <0x1>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,sja1105t";
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/* 12 MHz */
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spi-max-frequency = <12000000>;
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/* Sample data on trailing clock edge */
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spi-cpha;
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/* SPI controller settings for SJA1105 timing requirements */
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fsl,spi-cs-sck-delay = <1000>;
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fsl,spi-sck-cs-delay = <1000>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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swp5: port@0 {
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/* ETH5 written on chassis */
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label = "swp5";
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phy-handle = <&rgmii_phy6>;
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phy-mode = "rgmii-id";
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reg = <0>;
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};
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swp2: port@1 {
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/* ETH2 written on chassis */
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label = "swp2";
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phy-handle = <&rgmii_phy3>;
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phy-mode = "rgmii-id";
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reg = <1>;
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};
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swp3: port@2 {
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/* ETH3 written on chassis */
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label = "swp3";
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phy-handle = <&rgmii_phy4>;
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phy-mode = "rgmii-id";
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reg = <2>;
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};
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swp4: port@3 {
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/* ETH4 written on chassis */
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label = "swp4";
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phy-handle = <&rgmii_phy5>;
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phy-mode = "rgmii-id";
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reg = <3>;
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};
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port@4 {
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/* Internal port connected to eth2 */
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ethernet = <&enet2>;
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phy-mode = "rgmii";
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reg = <4>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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};
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&enet0 {
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tbi-handle = <&tbi0>;
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phy-handle = <&sgmii_phy2>;
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phy-mode = "sgmii";
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status = "okay";
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};
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&enet1 {
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tbi-handle = <&tbi1>;
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phy-handle = <&sgmii_phy1>;
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phy-mode = "sgmii";
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status = "okay";
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};
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/* RGMII delays added via PCB traces */
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&enet2 {
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phy-mode = "rgmii";
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status = "okay";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&i2c0 {
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status = "okay";
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};
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&mdio0 {
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/* AR8031 */
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sgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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/* AR8031 */
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sgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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/* BCM5464 quad PHY */
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rgmii_phy3: ethernet-phy@3 {
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reg = <0x3>;
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};
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rgmii_phy4: ethernet-phy@4 {
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reg = <0x4>;
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};
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rgmii_phy5: ethernet-phy@5 {
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reg = <0x5>;
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};
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rgmii_phy6: ethernet-phy@6 {
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reg = <0x6>;
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};
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/* SGMII PCS for enet0 */
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tbi0: tbi-phy@1f {
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reg = <0x1f>;
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device_type = "tbi-phy";
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};
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};
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&mdio1 {
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/* SGMII PCS for enet1 */
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tbi1: tbi-phy@1f {
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reg = <0x1f>;
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device_type = "tbi-phy";
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};
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};
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&qspi {
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bus-num = <0>;
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status = "okay";
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flash@0 {
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compatible = "spi-flash";
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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&uart0 {
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status = "okay";
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};
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