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https://github.com/AsahiLinux/u-boot
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fe133eb192
Add i.MX8QM qmx8 congatec board support U-Boot 2021.07-rc3-00528-gc9a966d9dd (May 31 2021 - 15:21:25 +0200) CPU: NXP i.MX8QM RevB A53 at 1200 MHz Model: Congatec QMX8 Qseven series Board: conga-QMX8 Build: SCFW 494c97f3, SECO-FW d63fdb21, ATF 09c5cc9 Boot: SD2 DRAM: 6 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 switch to partitions #0, OK mmc2 is current device Net: Error: ethernet@5b040000 address not set. No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
404 lines
11 KiB
Text
404 lines
11 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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* Copyright 2017 congatec AG
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* Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
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*/
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/dts-v1/;
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/* First 128KB is for PSCI ATF. */
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/memreserve/ 0x80000000 0x00020000;
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#include "fsl-imx8qm.dtsi"
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/ {
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model = "Congatec QMX8 Qseven series";
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compatible = "fsl,imx8qm-qmx8", "fsl,imx8qm";
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chosen {
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bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
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stdout-path = &lpuart0;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usdhc2_vmmc: usdhc2_vmmc {
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compatible = "regulator-fixed";
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regulator-name = "sw-3p3-sd1";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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off-on-delay-us = <3000>;
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};
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reg_usdhc3_vmmc: usdhc3_vmmc {
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compatible = "regulator-fixed";
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regulator-name = "sw-3p3-sd2";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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off-on-delay-us = <3000>;
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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fsl,rgmii_txc_dly;
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fsl,rgmii_rxc_dly;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@6 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <6>;
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at803x,eee-disabled;
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at803x,vddio-1p8v;
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};
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};
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};
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&gpio2 {
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status = "okay";
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};
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&gpio5 {
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status = "okay";
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};
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&i2c0 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c0>;
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clock-frequency = <100000>;
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status = "okay";
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rtc_ext: m41t62@68 {
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compatible = "st,m41t62";
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reg = <0x68>;
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};
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};
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&i2c1 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c1>;
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status = "okay";
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wm8904: wm8904@1a {
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compatible = "wlf,wm8904";
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reg = <0x1a>;
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clocks = <&clk IMX8QM_AUD_MCLKOUT0>;
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clock-names = "mclk";
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wlf,shared-lrclk;
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/* power-domains = <&pd_mclk_out0>; */
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assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
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<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
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<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
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<&clk IMX8QM_AUD_MCLKOUT0>;
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assigned-clock-rates = <786432000>, <49152000>, <24576000>;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx8qm-qmx8 {
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pinctrl_hog: hoggrp{
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fsl,pins = <
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SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 0x00000021
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SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021
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SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 0x00000021
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SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021
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SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021
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SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31 0x00000021
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SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021
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SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00 0x00000021
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SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
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SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
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SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
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SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
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SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
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SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
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SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
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SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
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SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
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SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
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SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
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SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
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SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
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SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
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>;
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};
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pinctrl_lpi2c0: lpi2c0grp {
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fsl,pins = <
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SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c
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SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c
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>;
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};
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pinctrl_lpi2c1: lpi2c1grp {
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fsl,pins = <
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SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c
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SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c
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>;
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};
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pinctrl_lpuart0: lpuart0grp {
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fsl,pins = <
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SC_P_UART0_RX_DMA_UART0_RX 0x06000020
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SC_P_UART0_TX_DMA_UART0_TX 0x06000020
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>;
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};
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pinctrl_lpuart1: lpuart1grp {
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fsl,pins = <
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SC_P_UART1_RX_DMA_UART1_RX 0x06000020
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SC_P_UART1_TX_DMA_UART1_TX 0x06000020
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SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020
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SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020
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>;
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};
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pinctrl_lpuart3: lpuart3grp {
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fsl,pins = <
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SC_P_M41_GPIO0_00_DMA_UART3_RX 0x06000020
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SC_P_M41_GPIO0_01_DMA_UART3_TX 0x06000020
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>;
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};
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pinctrl_mlb: mlbgrp {
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fsl,pins = <
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SC_P_MLB_SIG_CONN_MLB_SIG 0x21
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SC_P_MLB_CLK_CONN_MLB_CLK 0x21
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SC_P_MLB_DATA_CONN_MLB_DATA 0x21
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>;
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};
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pinctrl_isl29023: isl29023grp {
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fsl,pins = <
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SC_P_ADC_IN2_LSIO_GPIO3_IO20 0x00000021
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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fsl,pins = <
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SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
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SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
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SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
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>;
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};
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pinctrl_usdhc3_gpio: usdhc3grpgpio {
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fsl,pins = <
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SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x00000021
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SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
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SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
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SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
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SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
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SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
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SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
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SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
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>;
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};
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pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
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fsl,pins = <
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SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
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SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
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SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
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SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
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SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
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SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
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SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
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>;
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};
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pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
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fsl,pins = <
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SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
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SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
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SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
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SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
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SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
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SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
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SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
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>;
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};
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};
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};
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&lpuart0 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart0>;
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status = "okay";
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};
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&lpuart1 { /* Q7 connector */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart1>;
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status = "okay";
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};
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&pd_dma_lpuart0 {
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debug_console;
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
|
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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|
bus-width = <4>;
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|
cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
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|
wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
|
|
vmmc-supply = <®_usdhc2_vmmc>;
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|
fsl,tuning-start-tap = <20>;
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|
fsl,tuning-step= <2>;
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|
status = "okay";
|
|
};
|
|
|
|
&usdhc3 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
|
|
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
|
|
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
|
|
bus-width = <4>;
|
|
cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
|
|
vmmc-supply = <®_usdhc3_vmmc>;
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step= <2>;
|
|
status = "okay";
|
|
};
|