mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 11:00:15 +00:00
ef99f3d9e8
Add initial support for Google's Coral Dev Board based on i.MX8MQ. https://coral.ai/products/dev-board The Phanbell naming has been used here to match the naming convention used in Google's U-Boot source tree: https://coral.googlesource.com/uboot-imx/ Co-developed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com> Tested-by: Marco Franchi <marcofrk@gmail.com>
417 lines
9.8 KiB
Text
417 lines
9.8 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
|
/*
|
|
* Copyright 2020 NXP
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "imx8mq.dtsi"
|
|
|
|
/ {
|
|
model = "Google i.MX8MQ Phanbell";
|
|
compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
|
|
|
|
chosen {
|
|
stdout-path = &uart1;
|
|
};
|
|
|
|
memory@40000000 {
|
|
device_type = "memory";
|
|
reg = <0x00000000 0x40000000 0 0x40000000>;
|
|
};
|
|
|
|
pmic_osc: clock-pmic {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
clock-output-names = "pmic_osc";
|
|
};
|
|
|
|
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "VSD_3V3";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
};
|
|
};
|
|
|
|
&A53_0 {
|
|
cpu-supply = <&buck2>;
|
|
};
|
|
|
|
&A53_1 {
|
|
cpu-supply = <&buck2>;
|
|
};
|
|
|
|
&A53_2 {
|
|
cpu-supply = <&buck2>;
|
|
};
|
|
|
|
&A53_3 {
|
|
cpu-supply = <&buck2>;
|
|
};
|
|
|
|
&i2c1 {
|
|
clock-frequency = <400000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c1>;
|
|
status = "okay";
|
|
|
|
pmic: pmic@4b {
|
|
compatible = "rohm,bd71837";
|
|
reg = <0x4b>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pmic>;
|
|
#clock-cells = <0>;
|
|
clocks = <&pmic_osc>;
|
|
clock-output-names = "pmic_clk";
|
|
interrupt-parent = <&gpio1>;
|
|
interrupts = <3 GPIO_ACTIVE_LOW>;
|
|
|
|
regulators {
|
|
buck1: BUCK1 {
|
|
regulator-name = "buck1";
|
|
regulator-min-microvolt = <700000>;
|
|
regulator-max-microvolt = <1300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
regulator-ramp-delay = <1250>;
|
|
rohm,dvs-run-voltage = <900000>;
|
|
rohm,dvs-idle-voltage = <900000>;
|
|
rohm,dvs-suspend-voltage = <800000>;
|
|
};
|
|
|
|
buck2: BUCK2 {
|
|
regulator-name = "buck2";
|
|
regulator-min-microvolt = <850000>;
|
|
regulator-max-microvolt = <1000000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
rohm,dvs-run-voltage = <1000000>;
|
|
rohm,dvs-idle-voltage = <900000>;
|
|
};
|
|
|
|
buck3: BUCK3 {
|
|
regulator-name = "buck3";
|
|
regulator-min-microvolt = <700000>;
|
|
regulator-max-microvolt = <1300000>;
|
|
regulator-boot-on;
|
|
rohm,dvs-run-voltage = <900000>;
|
|
};
|
|
|
|
buck4: BUCK4 {
|
|
regulator-name = "buck4";
|
|
regulator-min-microvolt = <700000>;
|
|
regulator-max-microvolt = <1300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
rohm,dvs-run-voltage = <900000>;
|
|
};
|
|
|
|
buck5: BUCK5 {
|
|
regulator-name = "buck5";
|
|
regulator-min-microvolt = <700000>;
|
|
regulator-max-microvolt = <1350000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
buck6: BUCK6 {
|
|
regulator-name = "buck6";
|
|
regulator-min-microvolt = <3000000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
buck7: BUCK7 {
|
|
regulator-name = "buck7";
|
|
regulator-min-microvolt = <1605000>;
|
|
regulator-max-microvolt = <1995000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
buck8: BUCK8 {
|
|
regulator-name = "buck8";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1400000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo1: LDO1 {
|
|
regulator-name = "ldo1";
|
|
regulator-min-microvolt = <3000000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo2: LDO2 {
|
|
regulator-name = "ldo2";
|
|
regulator-min-microvolt = <900000>;
|
|
regulator-max-microvolt = <900000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo3: LDO3 {
|
|
regulator-name = "ldo3";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo4: LDO4 {
|
|
regulator-name = "ldo4";
|
|
regulator-min-microvolt = <900000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo5: LDO5 {
|
|
regulator-name = "ldo5";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo6: LDO6 {
|
|
regulator-name = "ldo6";
|
|
regulator-min-microvolt = <900000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo7: LDO7 {
|
|
regulator-name = "ldo7";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&fec1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_fec1>;
|
|
phy-mode = "rgmii-id";
|
|
phy-handle = <ðphy0>;
|
|
phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
|
|
phy-reset-duration = <10>;
|
|
phy-reset-post-delay = <50>;
|
|
fsl,magic-packet;
|
|
status = "okay";
|
|
|
|
mdio {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ethphy0: ethernet-phy@0 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&uart1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc1 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc1>;
|
|
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
|
bus-width = <8>;
|
|
non-removable;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc2 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
|
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
|
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
|
bus-width = <4>;
|
|
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
|
vmmc-supply = <®_usdhc2_vmmc>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usb3_phy0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb_dwc3_0 {
|
|
dr_mode = "otg";
|
|
status = "okay";
|
|
};
|
|
|
|
&usb3_phy1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb_dwc3_1 {
|
|
dr_mode = "host";
|
|
status = "okay";
|
|
};
|
|
|
|
&wdog1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_wdog>;
|
|
fsl,ext-reset-output;
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl_fec1: fec1grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
|
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
|
|
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
|
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
|
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
|
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
|
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
|
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
|
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
|
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
|
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
|
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
|
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
|
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
|
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
|
|
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
|
|
>;
|
|
};
|
|
|
|
pinctrl_pmic: pmicirq {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
|
|
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
|
|
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
|
|
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
|
|
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
|
|
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
|
|
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
|
|
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
|
|
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
|
|
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
|
|
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
|
|
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
|
|
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
|
|
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
|
|
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
|
|
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
|
|
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
|
|
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
|
|
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
|
|
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
|
|
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
|
|
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
|
|
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
|
|
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
|
|
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
|
|
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
|
|
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_gpio: usdhc2grpgpio {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
|
|
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
|
|
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
|
|
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
|
|
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
|
|
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
|
|
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
|
|
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
|
|
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
|
|
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
|
|
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
|
|
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
|
|
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
|
|
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
|
|
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
|
|
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
|
|
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
|
|
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
|
|
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
|
|
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
|
>;
|
|
};
|
|
};
|