mirror of
https://github.com/AsahiLinux/u-boot
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e72cb770d4
Device tree taken from Linux v5.16-rc5. Signed-off-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Fabio Estevam <festevam@gmail.com>
214 lines
4.2 KiB
Text
214 lines
4.2 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2019-2021 MNT Research GmbH
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* Copyright 2021 Lucas Stach <dev@lynxeye.de>
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*/
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/dts-v1/;
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#include "imx8mq-nitrogen-som.dtsi"
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/ {
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model = "MNT Reform 2";
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compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
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pcie1_refclk: clock-pcie1-refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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reg_main_5v: regulator-main-5v {
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compatible = "regulator-fixed";
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regulator-name = "5V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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reg_main_3v3: regulator-main-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reg_main_usb: regulator-main-usb {
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compatible = "regulator-fixed";
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regulator-name = "USB_PWR";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <®_main_5v>;
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};
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sound {
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compatible = "fsl,imx-audio-wm8960";
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audio-cpu = <&sai2>;
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audio-codec = <&wm8960>;
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audio-routing =
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"Headphone Jack", "HP_L",
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"Headphone Jack", "HP_R",
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"Ext Spk", "SPK_LP",
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"Ext Spk", "SPK_LN",
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"Ext Spk", "SPK_RP",
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"Ext Spk", "SPK_RN",
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"LINPUT1", "Mic Jack",
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"Mic Jack", "MICB",
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"LINPUT2", "Line In Jack",
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"RINPUT2", "Line In Jack";
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model = "wm8960-audio";
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};
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};
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&fec1 {
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status = "okay";
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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wm8960: codec@1a {
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compatible = "wlf,wm8960";
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reg = <0x1a>;
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clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
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clock-names = "mclk";
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#sound-dai-cells = <0>;
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};
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rtc@68 {
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compatible = "nxp,pcf8523";
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reg = <0x68>;
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};
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};
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&pcie1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie1>;
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reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
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clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
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<&clk IMX8MQ_CLK_PCIE2_AUX>,
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<&clk IMX8MQ_CLK_PCIE2_PHY>,
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<&pcie1_refclk>;
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clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
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status = "okay";
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};
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®_1p8v {
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vin-supply = <®_main_5v>;
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};
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®_snvs {
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vin-supply = <®_main_5v>;
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};
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®_arm_dram {
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vin-supply = <®_main_5v>;
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};
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®_dram_1p1v {
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vin-supply = <®_main_5v>;
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};
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®_soc_gpu_vpu {
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vin-supply = <®_main_5v>;
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};
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&sai2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai2>;
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assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
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assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
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assigned-clock-rates = <25000000>;
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fsl,sai-mclk-direction-output;
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fsl,sai-asynchronous;
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status = "okay";
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};
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&snvs_rtc {
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status = "disabled";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&usb3_phy0 {
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vbus-supply = <®_main_usb>;
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status = "okay";
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};
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&usb3_phy1 {
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vbus-supply = <®_main_usb>;
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status = "okay";
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};
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&usb_dwc3_0 {
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dr_mode = "host";
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status = "okay";
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};
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&usb_dwc3_1 {
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dr_mode = "host";
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status = "okay";
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};
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&usdhc2 {
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assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
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assigned-clock-rates = <200000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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vqmmc-supply = <®_main_3v3>;
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vmmc-supply = <®_main_3v3>;
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bus-width = <4>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
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>;
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};
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pinctrl_pcie1: pcie1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x16
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>;
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};
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pinctrl_sai2: sai2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
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MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6
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MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
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MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
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MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6
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MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
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MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
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MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
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>;
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};
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};
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