mirror of
https://github.com/AsahiLinux/u-boot
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6c3373b386
Add board dts for Advantech's imx8mp-rsb3720-a1 Signed-off-by: Darren Huang <darren.huang@advantech.com.tw> Signed-off-by: Kevin12.Chen <Kevin12.Chen@advantech.com.tw> Signed-off-by: Phill.Liu <Phill.Liu@advantech.com.tw> Signed-off-by: Tim Liang <tim.liang@advantech.com.tw> Signed-off-by: wei.zeng <wei.zeng@advantech.com.cn> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: uboot-imx <uboot-imx@nxp.com>
805 lines
19 KiB
Text
805 lines
19 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2019 NXP
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* Copyright 2022 Linaro
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*/
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/dts-v1/;
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#include <dt-bindings/usb/pd.h>
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#include "imx8mp.dtsi"
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/ {
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model = "Advantech i.MX8MPlus RSB3720A1 board";
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compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
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aliases {
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rtc0 = &s35390a;
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rtc1 = &snvs_rtc;
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};
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chosen {
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stdout-path = &uart3;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0 0xc0000000>,
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<0x1 0x00000000 0 0xc0000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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rpmsg_reserved: rpmsg@0x55800000 {
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no-map;
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reg = <0 0x55800000 0 0x800000>;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_led>;
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user {
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label = "user";
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gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
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default-state = "off"; /* LED BLUE */
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};
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};
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reg_usb1_host_vbus: regulator-usb1-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb1_host_vbus";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1_vbus>;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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reg_usdhc1_vmmc: regulator-usdhc1 {
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compatible = "regulator-fixed";
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regulator-name = "WLAN_EN";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100>;
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off-on-delay-us = <12000>;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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//gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100>;
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off-on-delay-us = <12000>;
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};
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lvds_backlight0: lvds_backlight@0 {
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compatible = "pwm-backlight";
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pwms = <&pwm2 0 5000000>;
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status = "disabled";
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brightness-levels = < 0 1 2 3 4 5 6 7 8 9
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10 11 12 13 14 15 16 17 18 19
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20 21 22 23 24 25 26 27 28 29
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30 31 32 33 34 35 36 37 38 39
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40 41 42 43 44 45 46 47 48 49
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50 51 52 53 54 55 56 57 58 59
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60 61 62 63 64 65 66 67 68 69
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70 71 72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87 88 89
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90 91 92 93 94 95 96 97 98 99
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100>;
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default-brightness-level = <80>;
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};
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lvds_backlight1: lvds_backlight@1 {
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compatible = "pwm-backlight";
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pwms = <&pwm3 0 5000000>;
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status = "disabled";
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brightness-levels = < 0 1 2 3 4 5 6 7 8 9
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10 11 12 13 14 15 16 17 18 19
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20 21 22 23 24 25 26 27 28 29
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30 31 32 33 34 35 36 37 38 39
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40 41 42 43 44 45 46 47 48 49
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50 51 52 53 54 55 56 57 58 59
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60 61 62 63 64 65 66 67 68 69
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70 71 72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87 88 89
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90 91 92 93 94 95 96 97 98 99
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100>;
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default-brightness-level = <80>;
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};
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rtl8367 {
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compatible = "realtek,rtl8367b";
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pinctrl-names = "default";
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gpio-sda = <&gpio5 10 GPIO_ACTIVE_HIGH>;
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gpio-sck = <&gpio5 11 GPIO_ACTIVE_HIGH>;
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realtek,extif0 = <1 0 1 1 1 1 1 1 2>;
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};
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};
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&clk {
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init-on-array = <IMX8MP_CLK_HSIO_ROOT>;
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};
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&A53_0 {
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cpu-supply = <&buck2_reg>;
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};
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&pwm2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm2>;
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status = "okay";
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};
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&pwm3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm3>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy1>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <4>;
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at803x,eee-disabled;
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at803x,vddio-1p8v;
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
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status = "okay";
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pmic: pca9450@25 {
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reg = <0x25>;
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compatible = "nxp,pca9450c", "nxp,pca9450b", "nxp,pca9450";
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/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
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pinctrl-0 = <&pinctrl_pmic>;
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gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
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regulators {
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#address-cells = <1>;
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#size-cells = <0>;
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pca9450,pmic-buck2-uses-i2c-dvs;
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/* Run/Standby voltage */
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pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
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buck1_reg: regulator@0 {
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reg = <0>;
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regulator-compatible = "buck1";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <2187500>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck2_reg: regulator@1 {
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reg = <1>;
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regulator-compatible = "buck2";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <2187500>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck4_reg: regulator@3 {
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reg = <3>;
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regulator-compatible = "buck4";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck5_reg: regulator@4 {
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reg = <4>;
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regulator-compatible = "buck5";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck6_reg: regulator@5 {
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reg = <5>;
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regulator-compatible = "buck6";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1_reg: regulator@6 {
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reg = <6>;
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regulator-compatible = "ldo1";
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regulator-min-microvolt = <1600000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo2_reg: regulator@7 {
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reg = <7>;
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regulator-compatible = "ldo2";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1150000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo3_reg: regulator@8 {
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reg = <8>;
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regulator-compatible = "ldo3";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo4_reg: regulator@9 {
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reg = <9>;
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regulator-compatible = "ldo4";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo5_reg: regulator@10 {
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reg = <10>;
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regulator-compatible = "ldo5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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s35390a: s35390a@30 {
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compatible = "sii,s35390a", "sii,s35392a";
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reg = <0x30>;
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status = "okay";
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};
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gpio_exp2: tca9538@71 {
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compatible = "nxp,pca9538";
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reg = <0x71>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio_exp1: tca9538@70 {
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compatible = "nxp,pca9538";
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reg = <0x70>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c3>;
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pinctrl-1 = <&pinctrl_i2c3_gpio>;
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scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
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status = "okay";
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pca6416: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&i2c4 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c4>;
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pinctrl-1 = <&pinctrl_i2c4_gpio>;
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scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
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status = "okay";
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24c02@50 {
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compatible = "fsl,24c02";
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reg = <0x50>;
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};
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};
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&snvs_pwrkey {
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status = "okay";
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};
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "okay";
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};
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&flexcan2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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status = "okay";
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};
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&uart1 { /* BT */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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assigned-clocks = <&clk IMX8MP_CLK_UART1>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
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fsl,uart-has-rtscts;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&uart3 {
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/* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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assigned-clocks = <&clk IMX8MP_CLK_UART3>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
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fsl,uart-has-rtscts;
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status = "okay";
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>;
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status = "okay";
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};
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&usb3_phy0 {
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fsl,phy-tx-vref-tune = <6>;
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fsl,phy-tx-rise-tune = <0>;
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fsl,phy-tx-preemp-amp-tune = <3>;
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fsl,phy-comp-dis-tune = <7>;
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fsl,pcs-tx-deemph-3p5db = <0x21>;
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fsl,phy-pcs-tx-swing-full = <0x7f>;
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status = "okay";
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};
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&usb3_0 {
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status = "okay";
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};
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&usb_dwc3_0 {
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dr_mode = "host";
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status = "okay";
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};
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&usb3_phy1 {
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fsl,phy-tx-preemp-amp-tune = <2>;
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status = "okay";
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};
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&usb3_1 {
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status = "okay";
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};
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&usb_dwc3_1 {
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dr_mode = "host";
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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bus-width = <4>;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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cqe-disabled;
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non-removable;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "disabled";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl_pwm2: pwm2grp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116
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>;
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};
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pinctrl_pwm3: pwm3grp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x116
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>;
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};
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
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MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
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MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
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MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
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MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
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MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
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MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
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MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
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MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
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MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
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MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
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MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
|
|
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
|
|
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
|
|
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_fec: fecgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
|
|
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
|
|
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
|
|
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
|
|
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
|
|
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
|
|
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
|
|
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
|
|
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
|
|
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
|
|
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
|
|
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
|
|
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
|
|
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
|
|
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexcan1: flexcan1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
|
|
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexcan2: flexcan2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
|
|
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexspi0: flexspi0grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
|
|
MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
|
|
MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
|
|
MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
|
|
MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
|
|
MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpio_led: gpioledgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
|
|
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
|
|
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3: i2c3grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
|
|
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c4: i2c4grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x400001c3
|
|
MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1_gpio: i2c1grp-gpio {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
|
|
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2_gpio: i2c2grp-gpio {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3
|
|
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3_gpio: i2c3grp-gpio {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3
|
|
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c4_gpio: i2c4_gpio_grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3
|
|
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_pmic: pmicirq {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
|
|
>;
|
|
};
|
|
|
|
pinctrl_sai2: sai2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
|
|
MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
|
|
MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
|
|
MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
|
|
>;
|
|
};
|
|
|
|
pinctrl_sai3: sai3grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
|
|
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
|
|
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
|
|
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
|
|
MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
|
|
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
|
|
MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
|
|
MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
|
|
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart3: uart3grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
|
|
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
|
|
MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
|
|
MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart4: uart4grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
|
|
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
|
|
>;
|
|
};
|
|
|
|
pinctrl_usb1_vbus: usb1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
|
|
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
|
|
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
|
|
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
|
|
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
|
|
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_gpio: usdhc1gpiogrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x19
|
|
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
|
|
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
|
|
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
|
|
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
|
|
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
|
|
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
|
|
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
|
|
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
|
|
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
|
|
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
|
|
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_gpio: usdhc2grp-gpio {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
|
|
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
|
|
>;
|
|
};
|
|
};
|