mirror of
https://github.com/AsahiLinux/u-boot
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9452d58e10
This patch converts the dart6ul ethernet support to DM_ETH and cleans up the legacy ethernet code. The clean up, more specifically: * moves the fec2 node and pin definition to the carrier board DTS since the phy associated with it is on the carrier board and not on the SoM; * add the reset pin associated to each phy; * separate the ethernet, mdio and reset pins of each fec so that they are easier to reference; * add clock properties to the phy nodes since they are connected to the 50Mhz ENET[12]_TX_CLK clock of the SoC; * remove CONFIG_BOARD_EARLY_INIT_F since the function is now empty. Signed-off-by: Marc Ferland <ferlandm@amotus.ca>
263 lines
5.9 KiB
Text
263 lines
5.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
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* Copyright (C) 2021 Marc Ferland, Amotus Solutions Inc., <ferlandm@amotus.ca>
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*/
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/ {
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model = "Variscite DART-6UL i.MX6 Ultra Low Lite SOM";
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compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
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memory {
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reg = <0x80000000 0x20000000>;
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};
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chosen {
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stdout-path = &uart1;
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};
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aliases {
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eeprom0 = &eeprom_som;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_rst &pinctrl_enet1_mdio>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <100>;
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status = "okay";
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mdio1: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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/* KSZ8081RNB (SoM) */
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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clocks = <&clks IMX6UL_CLK_ENET_REF>;
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clock-names = "rmii-ref";
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micrel,led-mode = <1>;
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max-speed = <100>;
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reg = <1>;
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};
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};
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};
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&gpio1 {
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u-boot,dm-pre-reloc;
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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nand-on-flash-bbt;
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fsl,no-blockmark-swap;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "uboot";
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reg = <0x0 0x400000>;
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};
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partition@400000 {
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label = "uboot-env";
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reg = <0x400000 0x100000>;
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};
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partition@500000 {
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label = "root";
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reg = <0x500000 0x0>;
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
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status = "okay";
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u-boot,dm-pre-reloc;
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eeprom_som: eeprom@50 {
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u-boot,dm-pre-reloc;
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compatible = "atmel,24c04";
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reg = <0x50>;
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status = "okay";
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};
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};
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&pwm1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm1>;
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#pwm-cells = <3>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
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bus-width = <0x4>;
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no-1-8-v;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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bus-width = <8>;
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no-1-8-v;
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non-removable;
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keep-power-in-suspend;
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status = "disabled";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
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>;
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};
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pinctrl_enet1_mdio: enet1-mdio-grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
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>;
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};
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pinctrl_gpmi_nand: gpminandgrp {
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fsl,pins = <
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MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x0b0b1
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MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
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MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
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MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
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MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
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MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
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MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0b0b1
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MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
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MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
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MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
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MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
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MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
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MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
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MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
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MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
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MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
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MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
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>;
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};
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pinctrl_i2c1: i2cgrp {
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fsl,pins = <
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MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
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MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
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>;
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};
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pinctrl_i2c1_gpio: i2c1grp_gpio {
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fsl,pins = <
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MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
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MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
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>;
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};
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pinctrl_i2c2: i2cgrp {
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u-boot,dm-pre-reloc;
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fsl,pins = <
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MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
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MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
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>;
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};
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pinctrl_i2c2_gpio: i2c2grp_gpio {
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u-boot,dm-pre-reloc;
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fsl,pins = <
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MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
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MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
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>;
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};
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pinctrl_pwm1: pwm1grp {
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fsl,pins = <
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MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x1b0b1
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
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MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
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MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
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MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
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MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
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MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
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MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
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>;
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};
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};
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&iomuxc_snvs {
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pinctrl_enet1_rst: enet1-rst-grp {
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fsl,pins = <
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MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0
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>;
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};
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};
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