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acb9a13b50
Add Gateworks Ventana dts/dtsi files from Linux 5.11 in preparation for conversion to driver-model. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
177 lines
4.7 KiB
Text
177 lines
4.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2013 Gateworks Corporation
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*/
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/dts-v1/;
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#include "imx6q.dtsi"
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#include "imx6qdl-gw54xx.dtsi"
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#include <dt-bindings/media/tda1997x.h>
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/ {
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model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX";
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compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
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sound-digital {
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compatible = "simple-audio-card";
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simple-audio-card,name = "tda1997x-audio";
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simple-audio-card,format = "i2s";
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simple-audio-card,bitclock-master = <&sound_codec>;
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simple-audio-card,frame-master = <&sound_codec>;
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sound_cpu: simple-audio-card,cpu {
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sound-dai = <&ssi2>;
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};
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sound_codec: simple-audio-card,codec {
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sound-dai = <&hdmi_receiver>;
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};
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};
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};
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&i2c3 {
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adv7180: camera@20 {
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compatible = "adi,adv7180";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_adv7180>;
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reg = <0x20>;
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powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&gpio3>;
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interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
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port {
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adv7180_to_ipu2_csi1_mux: endpoint {
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remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
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bus-width = <8>;
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};
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};
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};
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hdmi_receiver: hdmi-receiver@48 {
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compatible = "nxp,tda19971";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tda1997x>;
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reg = <0x48>;
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interrupt-parent = <&gpio1>;
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interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
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DOVDD-supply = <®_3p3v>;
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AVDD-supply = <&sw4_reg>;
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DVDD-supply = <&sw4_reg>;
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#sound-dai-cells = <0>;
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nxp,audout-format = "i2s";
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nxp,audout-layout = <0>;
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nxp,audout-width = <16>;
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nxp,audout-mclk-fs = <128>;
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/*
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* The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
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* and Y[11:4] across 16bits in the same cycle
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* which we map to VP[15:08]<->CSI_DATA[19:12]
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*/
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nxp,vidout-portcfg =
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/*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
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< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
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/*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
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< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
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/*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
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< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
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/*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
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< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
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port {
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tda1997x_to_ipu1_csi0_mux: endpoint {
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remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
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bus-width = <16>;
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hsync-active = <1>;
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vsync-active = <1>;
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data-active = <1>;
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};
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};
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};
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};
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&ipu1_csi0_from_ipu1_csi0_mux {
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bus-width = <16>;
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};
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&ipu1_csi0_mux_from_parallel_sensor {
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remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
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bus-width = <16>;
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};
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&ipu1_csi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu1_csi0>;
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};
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&ipu2_csi1_from_ipu2_csi1_mux {
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bus-width = <8>;
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};
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&ipu2_csi1_mux_from_parallel_sensor {
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remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
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bus-width = <8>;
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};
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&ipu2_csi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu2_csi1>;
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};
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&sata {
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status = "okay";
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};
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&iomuxc {
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pinctrl_adv7180: adv7180grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
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MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
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>;
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};
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pinctrl_ipu1_csi0: ipu1_csi0grp {
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fsl,pins = <
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MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0
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MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0
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MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0
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MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0
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MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0
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MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0
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MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0
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MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0
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MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
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MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
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MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
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MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
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MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
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MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
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MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
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MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
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MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
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MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
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MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
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>;
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};
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pinctrl_ipu2_csi1: ipu2_csi1grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0
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MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0
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MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0
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MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0
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MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0
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MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0
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MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0
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MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0
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MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0
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MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0
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MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0
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>;
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};
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pinctrl_tda1997x: tda1997xgrp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
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>;
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};
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};
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