mirror of
https://github.com/AsahiLinux/u-boot
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94c30f9c8f
As explained in commit 3bedbcc3aa
("arm: mvebu: a38x: serdes: Don't
overwrite read-only SAR PCIe registers") it is required to set Maximum Link
Width bits of PCIe Root Port Link Capabilities Register depending of number
of used serdes lanes. As this register is part of PCIe address space and
not serdes address space, move it into pci_mvebu.c driver.
Read number of PCIe lanes from DT property "num-lanes" which is used also
by other PCIe controller drivers in Linux kernel. If this property is
absent then it defaults to 1. This property needs to be set to 4 for every
mvebu board which use PEX_ROOT_COMPLEX_X4 or PEX_BUS_MODE_X4.
Enabling of PCIe port needs to be done afer all registers in PCIe address
space are properly configure. For this purpose use new mvebu-reset driver
(part of system-controller) and remove this code from serdes code.
Because some PCIe ports cannot be enabled individually, it is required to
first setup all PCIe ports and then enable them.
This change contains also all required "num-lanes" and "resets" DTS
properties, to make pci_mvebu.c driver work correctly.
Signed-off-by: Pali Rohár <pali@kernel.org>
219 lines
5.3 KiB
Text
219 lines
5.3 KiB
Text
/*
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* Device Tree file for Marvell Armada XP theadorable board
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*
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* Copyright (C) 2013-2014 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Note: this Device Tree assumes that the bootloader has remapped the
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* internal registers to 0xf1000000 (instead of the default
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* 0xd0000000). The 0xf1000000 is the default used by the recent,
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* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
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* boards were delivered with an older version of the bootloader that
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* left internal registers mapped at 0xd0000000. If you are in this
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* situation, you should either update your bootloader (preferred
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* solution) or the below Device Tree should be adjusted.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-xp-mv78260.dtsi"
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/ {
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model = "Marvell Armada XP theadorable";
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compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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spi0 = &spi0;
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spi1 = &spi1;
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ethernet0 = ð0;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
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internal-regs {
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serial@12000 {
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status = "okay";
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u-boot,dm-pre-reloc;
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};
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serial@12100 {
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status = "okay";
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};
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serial@12200 {
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status = "okay";
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};
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serial@12300 {
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status = "okay";
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};
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sata@a0000 {
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nr-ports = <2>;
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status = "okay";
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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ethernet@70000 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "sgmii";
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};
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usb@50000 {
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status = "okay";
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};
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usb@51000 {
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status = "okay";
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};
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/* The LCD controller is only used on this board */
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lcd0: lcd-controller@e0000 {
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compatible = "marvell,armada-xp-lcd";
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reg = <0xe0000 0x10000>;
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status = "okay";
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u-boot,dm-pre-reloc;
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display-timings {
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native-mode = <&timing0>;
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timing0: panel0 {
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hactive = <240>;
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vactive = <320>;
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hfront-porch = <1>;
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hback-porch = <45>;
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vfront-porch = <1>;
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vback-porch = <3>;
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/* Some dummy parameters */
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clock-frequency = <0>;
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hsync-len = <0>;
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vsync-len = <0>;
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};
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};
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};
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};
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};
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <100000>;
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <100000>;
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};
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&spi0 {
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status = "okay";
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u-boot,dm-pre-reloc;
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spi-flash@0 {
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q128a13", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <27777777>;
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};
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fpga@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-generic-device";
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reg = <1>; /* Chip select 1 */
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spi-max-frequency = <27777777>;
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};
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};
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&spi1 {
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status = "okay";
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fpga@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-generic-device";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <27777777>;
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};
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};
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&pciec {
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status = "okay";
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@9,0 {
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/* Port 2, Lane 0 */
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status = "okay";
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num-lanes = <4>;
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};
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};
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