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https://github.com/AsahiLinux/u-boot
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0e31666dfa
This is a range of stackable network switches. The SoC is Armada-385 and there are a number of variants with differing network port configurations. The DP variants are intended for a harsher operating environment so they use a different i2c mux and fit industrial-temp parts. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
266 lines
4.6 KiB
Text
266 lines
4.6 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-385.dtsi"
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/ {
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model = "Allied Telesis x530";
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compatible = "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
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chosen {
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stdout-path = "serial0:115200n8";
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bootargs = "console=ttyS0,115200 earlyprintk";
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};
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aliases {
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spi1 = &spi1;
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i2c0 = &i2c0;
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};
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memory {
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device_type = "memory";
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reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x3d) 0 0xf4800000 0x80000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
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pcie-mem-aperture = <0xa0000000 0x40000000>;
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};
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eco-button-interrupt {
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compatible = "atl,eco-button-interrupt";
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eco-button-gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;
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};
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board-reset {
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compatible = "atl,phy_reset";
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/* Physical board layout of reset pin is active-low but for the
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* current driver we have to set it to active-high here.
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*/
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phy-reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
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<&gpio1 21 GPIO_ACTIVE_HIGH>;
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};
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phy-int {
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compatible = "linux,uio-pdrv-genirq";
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interrupt-parent = <&gpio0>;
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interrupts = <6 IRQ_TYPE_EDGE_BOTH>;
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};
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led-enable {
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compatible = "atl,led-enable";
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led-enable-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
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};
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led_7seg {
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compatible = "atl,of-led-7seg";
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segment-gpios = <
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&led_7seg_gpio 0 0
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&led_7seg_gpio 1 0
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&led_7seg_gpio 2 0
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&led_7seg_gpio 3 0
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&led_7seg_gpio 4 0
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&led_7seg_gpio 5 0
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&led_7seg_gpio 6 0
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&led_7seg_gpio 7 0>;
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};
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poe {
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compatible = "atl,periph-poe";
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poe-reset-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
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interrupt-parent = <&gpio0>;
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interrupts = <20 IRQ_TYPE_EDGE_BOTH>;
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};
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};
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&pciec {
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status = "okay";
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};
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&pcie1 {
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status = "okay";
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};
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&devbus_cs1 {
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compatible = "marvell,mvebu-devbus";
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status = "okay";
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devbus,bus-width = <8>;
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devbus,turn-off-ps = <60000>;
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devbus,badr-skew-ps = <0>;
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devbus,acc-first-ps = <124000>;
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devbus,acc-next-ps = <248000>;
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devbus,rd-setup-ps = <0>;
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devbus,rd-hold-ps = <0>;
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/* Write parameters */
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devbus,sync-enable = <0>;
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devbus,wr-high-ps = <60000>;
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devbus,wr-low-ps = <60000>;
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devbus,ale-wr-ps = <60000>;
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nvs@0 {
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status = "okay";
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compatible = "mtd-ram";
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reg = <0 0x00080000>;
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bank-width = <1>;
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label = "nvs";
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};
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};
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&gpio0 {
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poe-disable {
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gpio-hog;
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gpios = <16 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "poe-disable";
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};
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};
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&gpio1 {
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poe-mezz-reset {
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gpio-hog;
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gpios = <15 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "poe-mezz-reset";
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};
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};
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&i2c0 {
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clock-frequency = <100000>;
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status = "okay";
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mux@71 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,pca9544";
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reg = <0x71>;
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i2c-mux-idle-disconnect;
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i2c@0 { /* POE devices MUX */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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rng@3b {
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compatible = "maxim,ds2476";
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reg = <0x3b>;
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};
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hwmon@2e {
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compatible = "adi,adt7476";
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reg = <0x2e>;
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};
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hwmon@2d {
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compatible = "adi,adt7476";
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reg = <0x2d>;
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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rtc@68 {
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compatible = "dallas,ds1340";
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reg = <0x68>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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led_7seg_gpio: gpio@20 {
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compatible = "nxp,pca9554";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x20>;
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};
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sfpgpio: gpio@27 { /* I2C to GPIO */
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compatible = "nxp,pca9555";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x27>;
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interrupt-parent = <&gpio0>;
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interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
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};
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sfpmux: mux@77 { /* SFP I2C MUX */
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,pca9544";
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reg = <0x77>;
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i2c-mux-idle-disconnect;
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};
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};
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};
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};
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&spi1 {
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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partition@u-boot {
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reg = <0x00000000 0x00100000>;
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label = "u-boot";
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};
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partition@u-boot-env {
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reg = <0x00100000 0x00040000>;
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label = "u-boot-env";
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};
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partition@unused {
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reg = <0x00140000 0x00e80000>;
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label = "unused";
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};
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partition@idprom {
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reg = <0x00fc0000 0x00040000>;
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label = "idprom";
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};
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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&refclk {
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clock-frequency = <25000000>;
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};
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&nand_controller { /* 256 MB */
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status = "okay";
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num-cs = <1>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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marvell,nand-enable-arbiter;
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nand-on-flash-bbt;
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};
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