mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
1d49b8d73b
Sync BeagleBone dts files & TPS dtsi files with Linux v5.17 and include the SanCloud BBE Extended WiFi dts added in v5.18-rc1. Also pull in changes to am33xx-l4.dtsi needed to support the BeagleBone Blue. The change to use the cpsw switch driver (commit c477358e66a3 in Linux) is excluded from the sync as u-boot does not recognise the new compatible string. Signed-off-by: Paul Barker <paul.barker@sancloud.com>
170 lines
2.8 KiB
Text
170 lines
2.8 KiB
Text
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "am33xx.dtsi"
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#include "am335x-bone-common.dtsi"
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#include "am335x-boneblack-common.dtsi"
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#include "am335x-boneblack-hdmi.dtsi"
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/ {
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model = "TI AM335x BeagleBone Black";
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compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
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};
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&cpu0_opp_table {
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/*
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* All PG 2.0 silicon may not support 1GHz but some of the early
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* BeagleBone Blacks have PG 2.0 silicon which is guaranteed
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* to support 1GHz OPP so enable it for PG 2.0 on this board.
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*/
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oppnitro-1000000000 {
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opp-supported-hw = <0x06 0x0100>;
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};
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};
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&gpio0 {
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gpio-line-names =
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"[mdio_data]",
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"[mdio_clk]",
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"P9_22 [spi0_sclk]",
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"P9_21 [spi0_d0]",
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"P9_18 [spi0_d1]",
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"P9_17 [spi0_cs0]",
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"[mmc0_cd]",
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"P8_42A [ecappwm0]",
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"P8_35 [lcd d12]",
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"P8_33 [lcd d13]",
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"P8_31 [lcd d14]",
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"P8_32 [lcd d15]",
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"P9_20 [i2c2_sda]",
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"P9_19 [i2c2_scl]",
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"P9_26 [uart1_rxd]",
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"P9_24 [uart1_txd]",
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"[rmii1_txd3]",
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"[rmii1_txd2]",
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"[usb0_drvvbus]",
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"[hdmi cec]",
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"P9_41B",
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"[rmii1_txd1]",
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"P8_19 [ehrpwm2a]",
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"P8_13 [ehrpwm2b]",
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"NC",
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"NC",
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"P8_14",
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"P8_17",
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"[rmii1_txd0]",
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"[rmii1_refclk]",
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"P9_11 [uart4_rxd]",
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"P9_13 [uart4_txd]";
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};
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&gpio1 {
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gpio-line-names =
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"P8_25 [mmc1_dat0]",
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"[mmc1_dat1]",
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"P8_5 [mmc1_dat2]",
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"P8_6 [mmc1_dat3]",
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"P8_23 [mmc1_dat4]",
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"P8_22 [mmc1_dat5]",
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"P8_3 [mmc1_dat6]",
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"P8_4 [mmc1_dat7]",
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"NC",
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"NC",
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"NC",
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"NC",
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"P8_12",
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"P8_11",
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"P8_16",
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"P8_15",
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"P9_15A",
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"P9_23",
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"P9_14 [ehrpwm1a]",
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"P9_16 [ehrpwm1b]",
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"[emmc rst]",
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"[usr0 led]",
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"[usr1 led]",
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"[usr2 led]",
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"[usr3 led]",
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"[hdmi irq]",
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"[usb vbus oc]",
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"[hdmi audio]",
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"P9_12",
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"P8_26",
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"P8_21 [emmc]",
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"P8_20 [emmc]";
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};
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&gpio2 {
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gpio-line-names =
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"P9_15B",
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"P8_18",
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"P8_7",
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"P8_8",
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"P8_10",
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"P8_9",
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"P8_45 [hdmi]",
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"P8_46 [hdmi]",
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"P8_43 [hdmi]",
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"P8_44 [hdmi]",
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"P8_41 [hdmi]",
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"P8_42 [hdmi]",
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"P8_39 [hdmi]",
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"P8_40 [hdmi]",
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"P8_37 [hdmi]",
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"P8_38 [hdmi]",
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"P8_36 [hdmi]",
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"P8_34 [hdmi]",
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"[rmii1_rxd3]",
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"[rmii1_rxd2]",
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"[rmii1_rxd1]",
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"[rmii1_rxd0]",
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"P8_27 [hdmi]",
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"P8_29 [hdmi]",
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"P8_28 [hdmi]",
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"P8_30 [hdmi]",
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"[mmc0_dat3]",
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"[mmc0_dat2]",
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"[mmc0_dat1]",
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"[mmc0_dat0]",
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"[mmc0_clk]",
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"[mmc0_cmd]";
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};
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&gpio3 {
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gpio-line-names =
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"[mii col]",
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"[mii crs]",
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"[mii rx err]",
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"[mii tx en]",
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"[mii rx dv]",
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"[i2c0 sda]",
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"[i2c0 scl]",
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"[jtag emu0]",
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"[jtag emu1]",
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"[mii tx clk]",
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"[mii rx clk]",
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"NC",
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"NC",
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"[usb vbus en]",
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"P9_31 [spi1_sclk]",
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"P9_29 [spi1_d0]",
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"P9_30 [spi1_d1]",
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"P9_28 [spi1_cs0]",
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"P9_42B [ecappwm0]",
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"P9_27",
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"P9_41A",
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"P9_25",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC",
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"NC";
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};
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