mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 02:38:56 +00:00
c7fad78ec0
This converts the following to Kconfig: CONFIG_SYS_BR0_PRELIM CONFIG_SYS_OR1_PRELIM CONFIG_SYS_BR1_PRELIM CONFIG_SYS_OR2_PRELIM CONFIG_SYS_BR2_PRELIM CONFIG_SYS_OR2_PRELIM CONFIG_SYS_BR3_PRELIM CONFIG_SYS_OR3_PRELIM CONFIG_SYS_BR4_PRELIM CONFIG_SYS_OR4_PRELIM CONFIG_SYS_BR5_PRELIM CONFIG_SYS_OR5_PRELIM CONFIG_SYS_BR6_PRELIM CONFIG_SYS_OR6_PRELIM CONFIG_SYS_BR7_PRELIM CONFIG_SYS_OR7_PRELIM This also introduces CONFIG_SYS_BR0_PRELIM_BOOL as not all platforms that can set these values do so. Add the relevant SYS_BRx_PRELIM_BOOL to platforms that had not been previously migrated. Signed-off-by: Tom Rini <trini@konsulko.com>
655 lines
20 KiB
C
655 lines
20 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* Copyright 2020 NXP
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*/
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/*
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* QorIQ RDB boards configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <linux/stringify.h>
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#if defined(CONFIG_TARGET_P1020RDB_PC)
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#define CONFIG_BOARDNAME "P1020RDB-PC"
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#define CONFIG_VSC7385_ENET
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#define CONFIG_SLIC
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#define __SW_BOOT_MASK 0x03
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#define __SW_BOOT_NOR 0x5c
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#define __SW_BOOT_SPI 0x1c
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#define __SW_BOOT_SD 0x9c
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#define __SW_BOOT_NAND 0xec
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#define __SW_BOOT_PCIE 0x6c
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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#endif
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/*
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* P1020RDB-PD board has user selectable switches for evaluating different
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* frequency and boot options for the P1020 device. The table that
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* follow describe the available options. The front six binary number was in
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* accordance with SW3[1:6].
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* 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
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* 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
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* 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
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* 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
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* 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
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* 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
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* 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
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*/
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#if defined(CONFIG_TARGET_P1020RDB_PD)
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#define CONFIG_BOARDNAME "P1020RDB-PD"
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#define CONFIG_VSC7385_ENET
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#define CONFIG_SLIC
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#define __SW_BOOT_MASK 0x03
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#define __SW_BOOT_NOR 0x64
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#define __SW_BOOT_SPI 0x34
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#define __SW_BOOT_SD 0x24
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#define __SW_BOOT_NAND 0x44
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#define __SW_BOOT_PCIE 0x74
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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/*
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* Dynamic MTD Partition support with mtdparts
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*/
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#endif
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#if defined(CONFIG_TARGET_P2020RDB)
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#define CONFIG_BOARDNAME "P2020RDB-PC"
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#define CONFIG_VSC7385_ENET
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#define __SW_BOOT_MASK 0x03
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#define __SW_BOOT_NOR 0xc8
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#define __SW_BOOT_SPI 0x28
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#define __SW_BOOT_SD 0x68 /* or 0x18 */
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#define __SW_BOOT_NAND 0xe8
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#define __SW_BOOT_PCIE 0xa8
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#define CONFIG_SYS_L2_SIZE (512 << 10)
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/*
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* Dynamic MTD Partition support with mtdparts
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*/
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#endif
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#ifdef CONFIG_SDCARD
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_PAD_TO 0x20000
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#define CONFIG_SPL_MAX_SIZE (128 * 1024)
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#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
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#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
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#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
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#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
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#define CONFIG_SYS_MPC85XX_NO_RESETVEC
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_COMMON_INIT_DDR
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#endif
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#elif defined(CONFIG_SPIFLASH)
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#define CONFIG_SPL_SPI_FLASH_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_PAD_TO 0x20000
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#define CONFIG_SPL_MAX_SIZE (128 * 1024)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
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#define CONFIG_SYS_MPC85XX_NO_RESETVEC
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_COMMON_INIT_DDR
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#endif
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#elif defined(CONFIG_MTD_RAW_NAND)
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#ifdef CONFIG_TPL_BUILD
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_NAND_INIT
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#define CONFIG_SPL_COMMON_INIT_DDR
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#define CONFIG_SPL_MAX_SIZE (128 << 10)
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#define CONFIG_TPL_TEXT_BASE 0xf8f81000
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#define CONFIG_SYS_MPC85XX_NO_RESETVEC
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
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#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
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#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
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#elif defined(CONFIG_SPL_BUILD)
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#define CONFIG_SPL_INIT_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_MAX_SIZE 4096
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
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#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
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#endif /* not CONFIG_TPL_BUILD */
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#define CONFIG_SPL_PAD_TO 0x20000
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#define CONFIG_TPL_PAD_TO 0x20000
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#endif
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#ifndef CONFIG_SYS_MONITOR_BASE
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#ifdef CONFIG_TPL_BUILD
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#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
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#elif defined(CONFIG_SPL_BUILD)
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
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#else
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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#endif
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#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
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#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
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#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
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#define CONFIG_SYS_SATA_MAX_DEVICE 2
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#define CONFIG_LBA48
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#if defined(CONFIG_TARGET_P2020RDB)
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#define CONFIG_SYS_CLK_FREQ 100000000
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#else
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#define CONFIG_SYS_CLK_FREQ 66666666
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#endif
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#define CONFIG_HWCONFIG
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE
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#define CONFIG_BTB
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#define CONFIG_ENABLE_36BIT_PHYS
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#define CONFIG_SYS_CCSRBAR 0xffe00000
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
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SPL code*/
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
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#endif
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/* DDR Setup */
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#define CONFIG_SYS_DDR_RAW_TIMING
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#define CONFIG_SYS_SPD_BUS_NUM 1
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#define SPD_EEPROM_ADDRESS 0x52
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#if defined(CONFIG_TARGET_P1020RDB_PD)
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#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
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#define CONFIG_CHIP_SELECTS_PER_CTRL 2
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#else
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#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
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#define CONFIG_CHIP_SELECTS_PER_CTRL 1
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#endif
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#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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/* Default settings for DDR3 */
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#ifndef CONFIG_TARGET_P2020RDB
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
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#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
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#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
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#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
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#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
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#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
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#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
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#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
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#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
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#define CONFIG_SYS_DDR_RCW_1 0x00000000
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#define CONFIG_SYS_DDR_RCW_2 0x00000000
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#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
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#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
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#define CONFIG_SYS_DDR_TIMING_4 0x00220001
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#define CONFIG_SYS_DDR_TIMING_5 0x03402400
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#define CONFIG_SYS_DDR_TIMING_3 0x00020000
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#define CONFIG_SYS_DDR_TIMING_0 0x00330004
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#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
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#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
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#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
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#define CONFIG_SYS_DDR_MODE_1 0x40461520
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#define CONFIG_SYS_DDR_MODE_2 0x8000c000
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#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
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#endif
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/*
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* Memory map
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*
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* 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
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* 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
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* 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
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* 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
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* (early boot only)
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* 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
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* 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
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* 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
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* 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
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* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
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* 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
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* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
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*/
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/*
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* Local Bus Definitions
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*/
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#if defined(CONFIG_TARGET_P1020RDB_PD)
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
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#define CONFIG_SYS_FLASH_BASE 0xec000000
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#else
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
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#define CONFIG_SYS_FLASH_BASE 0xef000000
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#endif
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
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#else
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#endif
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#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
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| BR_PS_16 | BR_V)
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#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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/* Nand Flash */
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#ifdef CONFIG_NAND_FSL_ELBC
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#define CONFIG_SYS_NAND_BASE 0xff800000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
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#else
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#endif
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8 bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V) /* valid */
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#if defined(CONFIG_TARGET_P1020RDB_PD)
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#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
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| OR_FCM_PGS /* Large Page*/ \
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| OR_FCM_CSCT \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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| OR_FCM_SCY_1 \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR)
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#else
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#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
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| OR_FCM_CSCT \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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| OR_FCM_SCY_1 \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR)
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#endif
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#endif /* CONFIG_NAND_FSL_ELBC */
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
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/* The assembler doesn't like typecast */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
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((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
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CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
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#else
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/* Initial L1 address */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
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#endif
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/* Size of used area in RAM */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
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#define CONFIG_SYS_CPLD_BASE 0xffa00000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
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#else
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#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
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#endif
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/* CPLD config size: 1Mb */
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#define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
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BR_PS_8 | BR_V)
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#define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
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#define CONFIG_SYS_PMC_BASE 0xff980000
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#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
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#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
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BR_PS_8 | BR_V)
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#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
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OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
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OR_GPCM_EAD)
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/* Vsc7385 switch */
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#ifdef CONFIG_VSC7385_ENET
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#define __VSCFW_ADDR "vscfw_addr=ef000000"
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#define CONFIG_SYS_VSC7385_BASE 0xffb00000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
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#else
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#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
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#endif
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#define CONFIG_SYS_VSC7385_BR_PRELIM \
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(BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
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#define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
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OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
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OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
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/* The size of the VSC7385 firmware image */
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#define CONFIG_VSC7385_IMAGE_SIZE 8192
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#endif
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/*
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* Config the L2 Cache as L2 SRAM
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*/
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#if defined(CONFIG_SPL_BUILD)
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#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
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#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
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#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
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#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
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#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
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#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
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#if defined(CONFIG_TARGET_P2020RDB)
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#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
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#else
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#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
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#endif
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#elif defined(CONFIG_MTD_RAW_NAND)
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#ifdef CONFIG_TPL_BUILD
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#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
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#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
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#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
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#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
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#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
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#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
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#else
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#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
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#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
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#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
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#endif /* CONFIG_TPL_BUILD */
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#endif
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#endif
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/* Serial Port - controlled on board with jumper J8
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* open - index 2
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* shorted - index 1
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*/
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
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#define CONFIG_NS16550_MIN_FUNCTIONS
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#endif
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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/* I2C */
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
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#endif
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#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
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/*
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* I2C2 EEPROM
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*/
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#define CONFIG_RTC_PT7C4338
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
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/* enable read and write access to EEPROM */
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#if defined(CONFIG_PCI)
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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/* controller 2, direct to uli, tgtid 2, Base address 9000 */
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
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#else
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
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#endif
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
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#else
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
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#endif
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/* controller 1, Slot 2, tgtid 1, Base address a000 */
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
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#else
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
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#endif
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
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#else
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
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#endif
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_TSEC1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC2
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#define CONFIG_TSEC2_NAME "eTSEC2"
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#define CONFIG_TSEC3
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#define CONFIG_TSEC3_NAME "eTSEC3"
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 0
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#define TSEC3_PHY_ADDR 1
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC3_PHYIDX 0
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#define CONFIG_ETHPRIME "eTSEC1"
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_HAS_ETH2
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#endif /* CONFIG_TSEC_ENET */
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/*
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* Environment
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*/
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#if defined(CONFIG_SDCARD)
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#define CONFIG_FSL_FIXED_MMC_LOCATION
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#elif defined(CONFIG_MTD_RAW_NAND)
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#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
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#ifdef CONFIG_TPL_BUILD
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#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
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#endif
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#elif defined(CONFIG_SYS_RAMBOOT)
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#define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#endif
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#define CONFIG_LOADS_ECHO /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
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/*
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* USB
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*/
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#define CONFIG_HAS_FSL_DR_USB
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#if defined(CONFIG_HAS_FSL_DR_USB)
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#ifdef CONFIG_USB_EHCI_HCD
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_USB_EHCI_FSL
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#endif
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#endif
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#if defined(CONFIG_TARGET_P1020RDB_PD)
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#endif
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#ifdef CONFIG_MMC
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#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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/*
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* Environment Configuration
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*/
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#define CONFIG_HOSTNAME "unknown"
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#define CONFIG_ROOTPATH "/opt/nfsroot"
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
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#ifdef __SW_BOOT_NOR
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#define __NOR_RST_CMD \
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norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
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i2c mw 18 3 __SW_BOOT_MASK 1; reset
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#endif
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#ifdef __SW_BOOT_SPI
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#define __SPI_RST_CMD \
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spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
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i2c mw 18 3 __SW_BOOT_MASK 1; reset
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#endif
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#ifdef __SW_BOOT_SD
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#define __SD_RST_CMD \
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sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
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i2c mw 18 3 __SW_BOOT_MASK 1; reset
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#endif
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#ifdef __SW_BOOT_NAND
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#define __NAND_RST_CMD \
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nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
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i2c mw 18 3 __SW_BOOT_MASK 1; reset
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#endif
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#ifdef __SW_BOOT_PCIE
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#define __PCIE_RST_CMD \
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pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
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i2c mw 18 3 __SW_BOOT_MASK 1; reset
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
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"loadaddr=1000000\0" \
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"bootfile=uImage\0" \
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"tftpflash=tftpboot $loadaddr $uboot; " \
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"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
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"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
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"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
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"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
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"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
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"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=2000000\0" \
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"ramdiskfile=rootfs.ext2.gz.uboot\0" \
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"fdtaddr=1e00000\0" \
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"bdev=sda1\0" \
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"jffs2nor=mtdblock3\0" \
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"norbootaddr=ef080000\0" \
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"norfdtaddr=ef040000\0" \
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"jffs2nand=mtdblock9\0" \
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"nandbootaddr=100000\0" \
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"nandfdtaddr=80000\0" \
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"ramdisk_size=120000\0" \
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"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
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"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
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__stringify(__VSCFW_ADDR)"\0" \
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__stringify(__NOR_RST_CMD)"\0" \
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__stringify(__SPI_RST_CMD)"\0" \
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__stringify(__SD_RST_CMD)"\0" \
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__stringify(__NAND_RST_CMD)"\0" \
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__stringify(__PCIE_RST_CMD)"\0"
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#define CONFIG_USB_FAT_BOOT \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs " \
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"ramdisk_size=$ramdisk_size;" \
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"usb start;" \
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"fatload usb 0:2 $loadaddr $bootfile;" \
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"fatload usb 0:2 $fdtaddr $fdtfile;" \
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"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_USB_EXT2_BOOT \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs " \
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"ramdisk_size=$ramdisk_size;" \
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"usb start;" \
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"ext2load usb 0:4 $loadaddr $bootfile;" \
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"ext2load usb 0:4 $fdtaddr $fdtfile;" \
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"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_NORBOOT \
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"setenv bootargs root=/dev/$jffs2nor rw " \
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"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
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"bootm $norbootaddr - $norfdtaddr"
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#endif /* __CONFIG_H */
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