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a537fa4da1
This driver support the standard PWM API for MediaTek MT7623, MT7622 and MT7629 SoCs Signed-off-by: Sam Shih <sam.shih@mediatek.com>
188 lines
4.6 KiB
C
188 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
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*
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <pwm.h>
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#include <div64.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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/* PWM registers and bits definitions */
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#define PWMCON 0x00
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#define PWMHDUR 0x04
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#define PWMLDUR 0x08
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#define PWMGDUR 0x0c
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#define PWMWAVENUM 0x28
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#define PWMDWIDTH 0x2c
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#define PWM45DWIDTH_FIXUP 0x30
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#define PWMTHRES 0x30
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#define PWM45THRES_FIXUP 0x34
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#define PWM_CLK_DIV_MAX 7
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#define MAX_PWM_NUM 8
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#define NSEC_PER_SEC 1000000000L
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static const unsigned int mtk_pwm_reg_offset[] = {
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0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
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};
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struct mtk_pwm_soc {
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unsigned int num_pwms;
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bool pwm45_fixup;
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};
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struct mtk_pwm_priv {
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void __iomem *base;
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struct clk top_clk;
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struct clk main_clk;
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struct clk pwm_clks[MAX_PWM_NUM];
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const struct mtk_pwm_soc *soc;
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};
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static void mtk_pwm_w32(struct udevice *dev, uint channel, uint reg, uint val)
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{
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struct mtk_pwm_priv *priv = dev_get_priv(dev);
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u32 offset = mtk_pwm_reg_offset[channel];
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writel(val, priv->base + offset + reg);
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}
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static int mtk_pwm_set_config(struct udevice *dev, uint channel,
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uint period_ns, uint duty_ns)
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{
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struct mtk_pwm_priv *priv = dev_get_priv(dev);
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u32 clkdiv = 0, clksel = 0, cnt_period, cnt_duty,
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reg_width = PWMDWIDTH, reg_thres = PWMTHRES;
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u64 resolution;
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int ret = 0;
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clk_enable(&priv->top_clk);
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clk_enable(&priv->main_clk);
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/* Using resolution in picosecond gets accuracy higher */
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resolution = (u64)NSEC_PER_SEC * 1000;
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do_div(resolution, clk_get_rate(&priv->pwm_clks[channel]));
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cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
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while (cnt_period > 8191) {
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resolution *= 2;
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clkdiv++;
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cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
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resolution);
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if (clkdiv > PWM_CLK_DIV_MAX && clksel == 0) {
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clksel = 1;
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clkdiv = 0;
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resolution = (u64)NSEC_PER_SEC * 1000 * 1625;
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do_div(resolution,
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clk_get_rate(&priv->pwm_clks[channel]));
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cnt_period = DIV_ROUND_CLOSEST_ULL(
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(u64)period_ns * 1000, resolution);
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clk_enable(&priv->pwm_clks[channel]);
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}
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}
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if (clkdiv > PWM_CLK_DIV_MAX && clksel == 1) {
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printf("pwm period %u not supported\n", period_ns);
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return -EINVAL;
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}
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if (priv->soc->pwm45_fixup && channel > 2) {
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/*
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* PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
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* from the other PWMs on MT7623.
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*/
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reg_width = PWM45DWIDTH_FIXUP;
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reg_thres = PWM45THRES_FIXUP;
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}
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cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
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if (clksel == 1)
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mtk_pwm_w32(dev, channel, PWMCON, BIT(15) | BIT(3) | clkdiv);
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else
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mtk_pwm_w32(dev, channel, PWMCON, BIT(15) | clkdiv);
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mtk_pwm_w32(dev, channel, reg_width, cnt_period);
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mtk_pwm_w32(dev, channel, reg_thres, cnt_duty);
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return ret;
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};
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static int mtk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
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{
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struct mtk_pwm_priv *priv = dev_get_priv(dev);
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u32 val = 0;
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val = readl(priv->base);
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if (enable)
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val |= BIT(channel);
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else
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val &= ~BIT(channel);
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writel(val, priv->base);
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return 0;
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};
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static int mtk_pwm_probe(struct udevice *dev)
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{
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struct mtk_pwm_priv *priv = dev_get_priv(dev);
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int ret = 0;
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int i;
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priv->soc = (struct mtk_pwm_soc *)dev_get_driver_data(dev);
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priv->base = (void __iomem *)devfdt_get_addr(dev);
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if (!priv->base)
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return -EINVAL;
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ret = clk_get_by_name(dev, "top", &priv->top_clk);
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if (ret < 0)
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return ret;
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ret = clk_get_by_name(dev, "main", &priv->main_clk);
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if (ret < 0)
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return ret;
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for (i = 0; i < priv->soc->num_pwms; i++) {
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char name[8];
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snprintf(name, sizeof(name), "pwm%d", i + 1);
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ret = clk_get_by_name(dev, name, &priv->pwm_clks[i]);
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if (ret < 0)
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return ret;
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}
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return ret;
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}
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static const struct pwm_ops mtk_pwm_ops = {
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.set_config = mtk_pwm_set_config,
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.set_enable = mtk_pwm_set_enable,
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};
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static const struct mtk_pwm_soc mt7622_data = {
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.num_pwms = 6,
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.pwm45_fixup = false,
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};
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static const struct mtk_pwm_soc mt7623_data = {
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.num_pwms = 5,
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.pwm45_fixup = true,
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};
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static const struct mtk_pwm_soc mt7629_data = {
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.num_pwms = 1,
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.pwm45_fixup = false,
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};
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static const struct udevice_id mtk_pwm_ids[] = {
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{ .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data },
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{ .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data },
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{ .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
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{ }
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};
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U_BOOT_DRIVER(mtk_pwm) = {
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.name = "mtk_pwm",
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.id = UCLASS_PWM,
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.of_match = mtk_pwm_ids,
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.ops = &mtk_pwm_ops,
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.probe = mtk_pwm_probe,
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.priv_auto_alloc_size = sizeof(struct mtk_pwm_priv),
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};
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