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https://github.com/AsahiLinux/u-boot
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d024236e5a
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
128 lines
3.2 KiB
C
128 lines
3.2 KiB
C
/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/armv8/mmu.h>
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/* Armada 7k/8k */
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#define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000))
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#define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84)
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#define RFU_SW_RESET_OFFSET 0
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/*
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* The following table includes all memory regions for Armada 7k and
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* 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets
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* define these regions at the beginning of the struct so that they
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* can be easier removed later dynamically if an Armada 7k device is detected.
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* For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt
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*/
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#define ARMADA_7K8K_COMMON_REGIONS_START 2
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static struct mm_region mvebu_mem_map[] = {
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/* Armada 80x0 memory regions include the CP1 (slave) units */
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{
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/* SRAM, MMIO regions - CP110 slave region */
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.phys = 0xf4000000UL,
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.virt = 0xf4000000UL,
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.size = 0x02000000UL, /* 32MiB internal registers */
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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{
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/* PCI CP1 regions */
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.phys = 0xfa000000UL,
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.virt = 0xfa000000UL,
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.size = 0x04000000UL, /* 64MiB CP110 slave PCI space */
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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/* Armada 80x0 and 70x0 common memory regions start here */
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{
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/* RAM */
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.phys = 0x0UL,
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.virt = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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},
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{
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/* SRAM, MMIO regions - AP806 region */
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.phys = 0xf0000000UL,
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.virt = 0xf0000000UL,
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.size = 0x01000000UL, /* 16MiB internal registers */
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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{
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/* SRAM, MMIO regions - CP110 master region */
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.phys = 0xf2000000UL,
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.virt = 0xf2000000UL,
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.size = 0x02000000UL, /* 32MiB internal registers */
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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{
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/* PCI CP0 regions */
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.phys = 0xf6000000UL,
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.virt = 0xf6000000UL,
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.size = 0x04000000UL, /* 64MiB CP110 master PCI space */
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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{
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0,
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}
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};
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struct mm_region *mem_map = mvebu_mem_map;
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void enable_caches(void)
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{
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/*
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* Armada 7k is not equipped with the CP110 slave CP. In case this
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* code runs on an Armada 7k device, lets remove the CP110 slave
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* entries from the memory mapping by moving the start to the
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* common regions.
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*/
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if (of_machine_is_compatible("marvell,armada7040"))
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mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START];
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icache_enable();
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dcache_enable();
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}
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void reset_cpu(ulong ignored)
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{
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u32 reg;
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reg = readl(RFU_GLOBAL_SW_RST);
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reg &= ~(1 << RFU_SW_RESET_OFFSET);
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writel(reg, RFU_GLOBAL_SW_RST);
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}
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/*
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* TODO - implement this functionality using platform
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* clock driver once it gets available
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* Return NAND clock in Hz
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*/
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u32 mvebu_get_nand_clock(void)
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{
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unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
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unsigned long NF_CLOCK_SEL_MASK = 0x1;
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u32 reg;
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reg = readl(NAND_FLASH_CLK_CTRL);
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if (reg & NF_CLOCK_SEL_MASK)
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return 400 * 1000000;
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else
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return 250 * 1000000;
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}
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