u-boot/board/xilinx
Selvamuthukumar 9b827cf172 Align end of bss by 4 bytes
Most of the bss initialization loop increments 4 bytes
at a time. And the loop end is checked for an 'equal'
condition. Make the bss end address aligned by 4, so
that the loop will end as expected.

Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-11-18 23:13:16 +01:00
..
common Big white-space cleanup. 2008-05-21 00:14:08 +02:00
ml300 Align end of bss by 4 bytes 2008-11-18 23:13:16 +01:00
ml401 Align end of bss by 4 bytes 2008-11-18 23:13:16 +01:00
ml507 ppc4xx: Add .gitignore file to xilinx-ppc440 boards 2008-09-12 07:11:48 +02:00
ppc405-generic ppc4xx: Generic architecture for xilinx ppc405(v3) 2008-10-24 17:26:09 +02:00
ppc440-generic Align end of bss by 4 bytes 2008-11-18 23:13:16 +01:00
xilinx_enet rename CFG_ENV_IS_NOWHERE in CONFIG_ENV_IS_NOWHERE 2008-09-10 22:48:00 +02:00
xilinx_iic rename CFG_ macros to CONFIG_SYS 2008-10-18 21:54:03 +02:00
xupv2p Align end of bss by 4 bytes 2008-11-18 23:13:16 +01:00