mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 18:28:55 +00:00
1a83f9931e
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com
9 lines
377 B
Text
9 lines
377 B
Text
config PHY_J721E_WIZ
|
|
tristate "TI J721E WIZ (SERDES Wrapper) support"
|
|
depends on ARCH_K3
|
|
help
|
|
This option enables support for WIZ module present in TI's J721E
|
|
SoC. WIZ is a serdes wrapper used to configure some of the input
|
|
signals to the SERDES (Sierra/Torrent). This driver configures
|
|
three clock selects (pll0, pll1, dig) and resets for each of the
|
|
lanes.
|