mirror of
https://github.com/AsahiLinux/u-boot
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53677ef18e
This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
412 lines
11 KiB
C
412 lines
11 KiB
C
/*
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* Copyright (c) 2001 Navin Boppuri / Prashant Patel
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* <nboppuri@trinetcommunication.com>,
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* <pmpatel@trinetcommunication.com>
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* Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de>
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* Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* MPC5xx CPM SPI interface.
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*
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* Parts of this code are probably not portable and/or specific to
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* the board which I used for the tests. Please send fixes/complaints
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* to wd@denx.de
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*
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* Ported to MPC5xx
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* Copyright (c) 2003 Denis Peter, MPL AG Switzerland, d.petr@mpl.ch.
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*/
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#include <common.h>
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#include <mpc5xx.h>
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#include <asm/5xx_immap.h>
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#include <linux/ctype.h>
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#include <malloc.h>
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#include <post.h>
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#include <net.h>
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#if defined(CONFIG_SPI)
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#undef DEBUG
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#define SPI_EEPROM_WREN 0x06
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#define SPI_EEPROM_RDSR 0x05
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#define SPI_EEPROM_READ 0x03
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#define SPI_EEPROM_WRITE 0x02
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#ifdef DEBUG
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#define DPRINT(a) printf a;
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/* -----------------------------------------------
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* Helper functions to peek into tx and rx buffers
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* ----------------------------------------------- */
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static const char * const hex_digit = "0123456789ABCDEF";
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static char quickhex (int i)
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{
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return hex_digit[i];
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}
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static void memdump (void *pv, int num)
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{
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int i;
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unsigned char *pc = (unsigned char *) pv;
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for (i = 0; i < num; i++)
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printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f));
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printf ("\t");
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for (i = 0; i < num; i++)
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printf ("%c", isprint (pc[i]) ? pc[i] : '.');
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printf ("\n");
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}
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#else /* !DEBUG */
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#define DPRINT(a)
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#endif /* DEBUG */
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/* -------------------
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* Function prototypes
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* ------------------- */
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void spi_init (void);
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ssize_t spi_read (uchar *, int, uchar *, int);
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ssize_t spi_write (uchar *, int, uchar *, int);
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ssize_t spi_xfer (size_t);
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/* **************************************************************************
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*
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* Function: spi_init_f
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*
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* Description: Init SPI-Controller (ROM part)
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*
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* return: ---
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*
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* *********************************************************************** */
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void spi_init_f (void)
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{
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int i;
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volatile immap_t *immr;
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volatile qsmcm5xx_t *qsmcm;
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immr = (immap_t *) CFG_IMMR;
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qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
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qsmcm->qsmcm_qsmcr = 0; /* all accesses enabled */
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qsmcm->qsmcm_qspi_il = 0; /* lowest IRQ */
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/* --------------------------------------------
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* GPIO or per. Function
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* PQSPAR[00] = 0 reserved
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* PQSPAR[01] = 1 [0x4000] -> PERI: (SPICS3)
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* PQSPAR[02] = 0 [0x0000] -> GPIO
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* PQSPAR[03] = 0 [0x0000] -> GPIO
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* PQSPAR[04] = 1 [0x0800] -> PERI: (SPICS0)
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* PQSPAR[05] = 0 reseved
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* PQSPAR[06] = 1 [0x0200] -> PERI: (SPIMOSI)
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* PQSPAR[07] = 1 [0x0100] -> PERI: (SPIMISO)
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* -------------------------------------------- */
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qsmcm->qsmcm_pqspar = 0x3 | (CFG_SPI_CS_USED << 3);
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/* --------------------------------------------
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* DDRQS[00] = 0 reserved
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* DDRQS[01] = 1 [0x0040] -> SPICS3 Output
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* DDRQS[02] = 0 [0x0000] -> GPIO Output
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* DDRQS[03] = 0 [0x0000] -> GPIO Output
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* DDRQS[04] = 1 [0x0008] -> SPICS0 Output
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* DDRQS[05] = 1 [0x0004] -> SPICLK Output
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* DDRQS[06] = 1 [0x0002] -> SPIMOSI Output
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* DDRQS[07] = 0 [0x0001] -> SPIMISO Input
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* -------------------------------------------- */
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qsmcm->qsmcm_ddrqs = 0x7E;
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/* --------------------------------------------
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* Base state for used SPI CS pins, if base = 0 active must be 1
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* PORTQS[00] = 0 reserved
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* PORTQS[01] = 0 reserved
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* PORTQS[02] = 0 reserved
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* PORTQS[03] = 0 reserved
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* PORTQS[04] = 0 [0x0000] RxD2
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* PORTQS[05] = 1 [0x0400] TxD2
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* PORTQS[06] = 0 [0x0000] RxD1
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* PORTQS[07] = 1 [0x0100] TxD1
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* PORTQS[08] = 0 reserved
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* PORTQS[09] = 0 [0x0000] -> SPICS3 Base Output
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* PORTQS[10] = 0 [0x0000] -> SPICS2 Base Output
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* PORTQS[11] = 0 [0x0000] -> SPICS1 Base Output
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* PORTQS[12] = 0 [0x0000] -> SPICS0 Base Output
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* PORTQS[13] = 0 [0x0004] -> SPICLK Output
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* PORTQS[14] = 0 [0x0002] -> SPIMOSI Output
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* PORTQS[15] = 0 [0x0001] -> SPIMISO Input
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* -------------------------------------------- */
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qsmcm->qsmcm_portqs |= (CFG_SPI_CS_BASE << 3);
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/* --------------------------------------------
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* Controll Register 0
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* SPCR0[00] = 1 (0x8000) Master
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* SPCR0[01] = 0 (0x0000) Wired-Or
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* SPCR0[2..5] = (0x2000) Bits per transfer (default 8)
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* SPCR0[06] = 0 (0x0000) Normal polarity
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* SPCR0[07] = 0 (0x0000) Normal Clock Phase
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* SPCR0[08..15] = 14 1.4MHz
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*/
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qsmcm->qsmcm_spcr0=0xA00E;
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/* --------------------------------------------
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* Controll Register 1
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* SPCR1[00] = 0 (0x0000) QSPI enabled
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* SPCR1[1..7] = (0x7F00) Delay before Transfer
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* SPCR1[8..15] = (0x0000) Delay After transfer (204.8usec@40MHz)
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*/
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qsmcm->qsmcm_spcr1=0x7F00;
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/* --------------------------------------------
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* Controll Register 2
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* SPCR2[00] = 0 (0x0000) SPI IRQs Disabeld
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* SPCR2[01] = 0 (0x0000) No Wrap around
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* SPCR2[02] = 0 (0x0000) Wrap to 0
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* SPCR2[3..7] = (0x0000) End Queue pointer = 0
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* SPCR2[8..10] = 0 (0x0000) reserved
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* SPCR2[11..15] = 0 (0x0000) NewQueue Address = 0
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*/
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qsmcm->qsmcm_spcr2=0x0000;
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/* --------------------------------------------
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* Controll Register 3
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* SPCR3[00..04] = 0 (0x0000) reserved
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* SPCR3[05] = 0 (0x0000) Feedback disabled
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* SPCR3[06] = 0 (0x0000) IRQ on HALTA & MODF disabled
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* SPCR3[07] = 0 (0x0000) Not halted
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*/
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qsmcm->qsmcm_spcr3=0x00;
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/* --------------------------------------------
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* SPSR (Controll Register 3) Read only/ reset Flags 08,09,10
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* SPCR3[08] = 1 (0x80) QSPI finished
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* SPCR3[09] = 1 (0x40) Mode Fault Flag
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* SPCR3[10] = 1 (0x20) HALTA
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* SPCR3[11..15] = 0 (0x0000) Last executed command
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*/
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qsmcm->qsmcm_spsr=0xE0;
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/*-------------------------------------------
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* Setup RAM
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*/
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for(i=0;i<32;i++) {
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qsmcm->qsmcm_recram[i]=0x0000;
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qsmcm->qsmcm_tranram[i]=0x0000;
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qsmcm->qsmcm_comdram[i]=0x00;
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}
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return;
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}
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/* **************************************************************************
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*
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* Function: spi_init_r
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* Dummy, all initializations have been done in spi_init_r
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* *********************************************************************** */
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void spi_init_r (void)
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{
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return;
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}
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/****************************************************************************
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* Function: spi_write
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**************************************************************************** */
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ssize_t short_spi_write (uchar *addr, int alen, uchar *buffer, int len)
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{
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int i,dlen;
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volatile immap_t *immr;
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volatile qsmcm5xx_t *qsmcm;
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immr = (immap_t *) CFG_IMMR;
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qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
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for(i=0;i<32;i++) {
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qsmcm->qsmcm_recram[i]=0x0000;
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qsmcm->qsmcm_tranram[i]=0x0000;
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qsmcm->qsmcm_comdram[i]=0x00;
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}
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qsmcm->qsmcm_tranram[0] = SPI_EEPROM_WREN; /* write enable */
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spi_xfer(1);
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i=0;
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qsmcm->qsmcm_tranram[i++] = SPI_EEPROM_WRITE; /* WRITE memory array */
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qsmcm->qsmcm_tranram[i++] = addr[0];
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qsmcm->qsmcm_tranram[i++] = addr[1];
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for(dlen=0;dlen<len;dlen++) {
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qsmcm->qsmcm_tranram[i+dlen] = buffer[dlen]; /* WRITE memory array */
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}
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/* transmit it */
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spi_xfer(i+dlen);
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/* ignore received data */
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for (i = 0; i < 1000; i++) {
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qsmcm->qsmcm_tranram[0] = SPI_EEPROM_RDSR; /* read status */
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qsmcm->qsmcm_tranram[1] = 0;
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spi_xfer(2);
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if (!(qsmcm->qsmcm_recram[1] & 1)) {
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break;
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}
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udelay(1000);
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}
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if (i >= 1000) {
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printf ("*** spi_write: Time out while writing!\n");
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}
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return len;
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}
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#define TRANSFER_LEN 16
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ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
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{
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int index,i,newlen;
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uchar newaddr[2];
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int curraddr;
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curraddr=(addr[alen-2]<<8)+addr[alen-1];
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i=len;
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index=0;
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do {
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newaddr[1]=(curraddr & 0xff);
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newaddr[0]=((curraddr>>8) & 0xff);
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if(i>TRANSFER_LEN) {
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newlen=TRANSFER_LEN;
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i-=TRANSFER_LEN;
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}
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else {
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newlen=i;
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i=0;
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}
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short_spi_write (newaddr, 2, &buffer[index], newlen);
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index+=newlen;
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curraddr+=newlen;
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}while(i);
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return (len);
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}
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/****************************************************************************
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* Function: spi_read
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**************************************************************************** */
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ssize_t short_spi_read (uchar *addr, int alen, uchar *buffer, int len)
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{
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int i;
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volatile immap_t *immr;
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volatile qsmcm5xx_t *qsmcm;
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immr = (immap_t *) CFG_IMMR;
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qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
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for(i=0;i<32;i++) {
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qsmcm->qsmcm_recram[i]=0x0000;
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qsmcm->qsmcm_tranram[i]=0x0000;
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qsmcm->qsmcm_comdram[i]=0x00;
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}
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i=0;
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qsmcm->qsmcm_tranram[i++] = (SPI_EEPROM_READ); /* READ memory array */
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qsmcm->qsmcm_tranram[i++] = addr[0] & 0xff;
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qsmcm->qsmcm_tranram[i++] = addr[1] & 0xff;
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spi_xfer(3 + len);
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for(i=0;i<len;i++) {
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*buffer++=(char)qsmcm->qsmcm_recram[i+3];
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}
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return len;
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}
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ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
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{
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int index,i,newlen;
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uchar newaddr[2];
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int curraddr;
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curraddr=(addr[alen-2]<<8)+addr[alen-1];
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i=len;
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index=0;
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do {
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newaddr[1]=(curraddr & 0xff);
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newaddr[0]=((curraddr>>8) & 0xff);
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if(i>TRANSFER_LEN) {
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newlen=TRANSFER_LEN;
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i-=TRANSFER_LEN;
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}
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else {
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newlen=i;
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i=0;
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}
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short_spi_read (newaddr, 2, &buffer[index], newlen);
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index+=newlen;
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curraddr+=newlen;
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}while(i);
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return (len);
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}
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/****************************************************************************
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* Function: spi_xfer
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**************************************************************************** */
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ssize_t spi_xfer (size_t count)
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{
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volatile immap_t *immr;
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volatile qsmcm5xx_t *qsmcm;
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int i;
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int tm;
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ushort status;
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immr = (immap_t *) CFG_IMMR;
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qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
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DPRINT (("*** spi_xfer entered count %d***\n",count));
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/* Set CS for device */
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for(i=0;i<(count-1);i++)
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qsmcm->qsmcm_comdram[i] = 0x80 | CFG_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */
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qsmcm->qsmcm_comdram[i] = CFG_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */
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qsmcm->qsmcm_spcr2=((count-1)&0x1F)<<8;
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DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", count));
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qsmcm->qsmcm_spsr=0xE0; /* clear all flags */
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/* start spi transfer */
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DPRINT (("*** spi_xfer: Performing transfer ...\n"));
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qsmcm->qsmcm_spcr1 |= 0x8000; /* Start transmit */
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/* --------------------------------
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* Wait for SPI transmit to get out
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* or time out (1 second = 1000 ms)
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* -------------------------------- */
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for (tm=0; tm<1000; ++tm) {
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status=qsmcm->qsmcm_spcr1;
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if((status & 0x8000)==0)
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break;
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udelay (1000);
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}
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if (tm >= 1000) {
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printf ("*** spi_xfer: Time out while xferring to/from SPI!\n");
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}
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#ifdef DEBUG
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printf ("\nspi_xfer: txbuf after xfer\n");
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memdump ((void *) qsmcm->qsmcm_tranram, 32); /* dump of txbuf before transmit */
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printf ("spi_xfer: rxbuf after xfer\n");
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memdump ((void *) qsmcm->qsmcm_recram, 32); /* dump of rxbuf after transmit */
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printf ("\nspi_xfer: commbuf after xfer\n");
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memdump ((void *) qsmcm->qsmcm_comdram, 32); /* dump of txbuf before transmit */
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printf ("\n");
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#endif
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return count;
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}
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#endif /* CONFIG_SPI */
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