mirror of
https://github.com/AsahiLinux/u-boot
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1c140f7bbf
icorem6qdl> mtdparts device nand0 <nand>, # parts = 6 0: spl 0x00200000 0x00000000 0 1: uboot 0x00200000 0x00200000 0 2: env 0x00100000 0x00400000 0 3: kernel 0x00400000 0x00500000 0 4: dtb 0x00100000 0x00900000 0 5: rootfs 0x1f600000 0x00a00000 0 Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
167 lines
4.2 KiB
C
167 lines
4.2 KiB
C
/*
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* Copyright (C) 2016 Amarula Solutions B.V.
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* Copyright (C) 2016 Engicam S.r.l.
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*
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* Configuration settings for the Engicam i.CoreM6 QDL Starter Kits.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __IMX6QLD_ICORE_CONFIG_H
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#define __IMX6QLD_ICORE_CONFIG_H
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#include <linux/sizes.h>
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#include "mx6_common.h"
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
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/* Total Size of Environment Sector */
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#define CONFIG_ENV_SIZE SZ_128K
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/* Allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* Environment */
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#ifndef CONFIG_ENV_IS_NOWHERE
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/* Environment in MMC */
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# if defined(CONFIG_ENV_IS_IN_MMC)
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# define CONFIG_ENV_OFFSET 0x100000
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/* Environment in NAND */
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# elif defined(CONFIG_ENV_IS_IN_NAND)
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# define CONFIG_ENV_OFFSET 0x400000
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# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
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# endif
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#endif
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/* Default environment */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"script=boot.scr\0" \
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"image=zImage\0" \
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"console=ttymxc3\0" \
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"fdt_high=0xffffffff\0" \
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"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"fdt_addr=0x18000000\0" \
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"boot_fdt=try\0" \
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"mmcdev=0\0" \
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"mmcpart=1\0" \
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"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} " \
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"root=${mmcroot}\0" \
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"loadbootscript=" \
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"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
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"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if run loadfdt; then " \
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"bootz ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"if test ${boot_fdt} = try; then " \
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"bootz; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"fi; " \
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"else " \
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"bootz; " \
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"fi\0"
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev};" \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loadimage; then " \
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"run mmcboot; " \
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"fi; " \
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"fi; " \
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"fi"
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_SYS_HZ 1000
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_SP_OFFSET)
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/* UART */
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#ifdef CONFIG_MXC_UART
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# define CONFIG_MXC_UART_BASE UART4_BASE
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#endif
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/* MMC */
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#ifdef CONFIG_FSL_USDHC
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# define CONFIG_SYS_MMC_ENV_DEV 0
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# define CONFIG_SYS_FSL_USDHC_NUM 1
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# define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
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#endif
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/* NAND */
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#ifdef CONFIG_NAND_MXS
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# define CONFIG_SYS_MAX_NAND_DEVICE 1
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# define CONFIG_SYS_NAND_BASE 0x40000000
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# define CONFIG_SYS_NAND_5_ADDR_CYCLE
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# define CONFIG_SYS_NAND_ONFI_DETECTION
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# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
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/* MTD device */
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# define CONFIG_MTD_DEVICE
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# define CONFIG_CMD_MTDPARTS
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# define CONFIG_MTD_PARTITIONS
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# define MTDIDS_DEFAULT "nand0=nand"
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# define MTDPARTS_DEFAULT "mtdparts=nand:2m(spl),2m(uboot)," \
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"1m(env),4m(kernel),1m(dtb),-(rootfs)"
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# define CONFIG_APBH_DMA
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# define CONFIG_APBH_DMA_BURST
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# define CONFIG_APBH_DMA_BURST8
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#endif
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/* Ethernet */
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#ifdef CONFIG_FEC_MXC
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# define IMX_FEC_BASE ENET_BASE_ADDR
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# define CONFIG_FEC_MXC_PHYADDR 0
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# define CONFIG_FEC_XCV_TYPE RMII
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# define CONFIG_ETHPRIME "FEC"
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# define CONFIG_MII
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# define CONFIG_PHYLIB
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# define CONFIG_PHY_SMSC
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#endif
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/* SPL */
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#ifdef CONFIG_SPL
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# ifdef CONFIG_NAND_MXS
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# define CONFIG_SPL_NAND_SUPPORT
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# else
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# define CONFIG_SPL_MMC_SUPPORT
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# endif
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# include "imx6_spl.h"
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# ifdef CONFIG_SPL_BUILD
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# undef CONFIG_DM_GPIO
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# undef CONFIG_DM_MMC
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# endif
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#endif
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#endif /* __IMX6QLD_ICORE_CONFIG_H */
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