mirror of
https://github.com/AsahiLinux/u-boot
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eceb4e006a
Explicitly configure GPIO0_0 in SPL, which controlls 3V3 voltage on the XEA board (it also supplies TIVAs). This code would enable TIVAs power supply early (also when board uses the falcon boot). Signed-off-by: Lukasz Majewski <lukma@denx.de>
200 lines
4 KiB
C
200 lines
4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* XEA iMX28 board
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*
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* Copyright (C) 2019 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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* Copyright (C) 2018 DENX Software Engineering
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* Måns Rullgård, DENX Software Engineering, mans@mansr.com
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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*/
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/mii.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <errno.h>
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#include <usb.h>
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#include <serial.h>
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#ifdef CONFIG_SPL_BUILD
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#include <spl.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Functions
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*/
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static void init_clocks(void)
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{
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/* IO0 clock at 480MHz */
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mxs_set_ioclk(MXC_IOCLK0, 480000);
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/* IO1 clock at 480MHz */
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mxs_set_ioclk(MXC_IOCLK1, 480000);
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/* SSP0 clock at 96MHz */
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mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
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/* SSP2 clock at 160MHz */
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mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
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/* SSP3 clock at 96MHz */
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mxs_set_sspclk(MXC_SSPCLK3, 96000, 0);
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}
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#ifdef CONFIG_SPL_BUILD
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void board_init_f(ulong arg)
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{
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init_clocks();
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preloader_console_init();
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}
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static int boot_tiva0, boot_tiva1;
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/* Check if TIVAs request booting via U-Boot proper */
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void spl_board_init(void)
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{
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struct gpio_desc btiva0, btiva1, en_3_3v;
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int ret;
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/*
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* Setup GPIO0_0 (TIVA power enable pin) to be output high
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* to allow TIVA startup.
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*/
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ret = dm_gpio_lookup_name("GPIO0_0", &en_3_3v);
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if (ret)
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printf("Cannot get GPIO0_0\n");
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ret = dm_gpio_request(&en_3_3v, "pwr_3_3v");
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if (ret)
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printf("Cannot request GPIO0_0\n");
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/* Set GPIO0_0 to HIGH */
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dm_gpio_set_dir_flags(&en_3_3v, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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ret = dm_gpio_lookup_name("GPIO0_23", &btiva0);
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if (ret)
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printf("Cannot get GPIO0_23\n");
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ret = dm_gpio_lookup_name("GPIO0_25", &btiva1);
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if (ret)
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printf("Cannot get GPIO0_25\n");
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ret = dm_gpio_request(&btiva0, "boot-tiva0");
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if (ret)
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printf("Cannot request GPIO0_23\n");
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ret = dm_gpio_request(&btiva1, "boot-tiva1");
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if (ret)
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printf("Cannot request GPIO0_25\n");
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dm_gpio_set_dir_flags(&btiva0, GPIOD_IS_IN);
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dm_gpio_set_dir_flags(&btiva1, GPIOD_IS_IN);
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udelay(1000);
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boot_tiva0 = dm_gpio_get_value(&btiva0);
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boot_tiva1 = dm_gpio_get_value(&btiva1);
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}
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void board_boot_order(u32 *spl_boot_list)
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{
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spl_boot_list[0] = BOOT_DEVICE_MMC1;
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spl_boot_list[1] = BOOT_DEVICE_SPI;
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}
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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if (serial_tstc() && serial_getc() == 'c')
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return 1;
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debug("%s: btiva0: %d btiva1: %d\n", __func__, boot_tiva0, boot_tiva1);
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return !boot_tiva0 || !boot_tiva1;
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}
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#else
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int board_early_init_f(void)
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{
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init_clocks();
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return 0;
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}
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int board_init(void)
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{
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struct gpio_desc phy_rst;
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int ret;
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/* Address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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cpu_eth_init(NULL);
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/* PHY INT#/PWDN# */
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ret = dm_gpio_lookup_name("GPIO4_13", &phy_rst);
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if (ret) {
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printf("Cannot get GPIO4_13\n");
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return ret;
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}
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ret = dm_gpio_request(&phy_rst, "phy-rst");
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if (ret) {
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printf("Cannot request GPIO4_13\n");
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return ret;
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}
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dm_gpio_set_dir_flags(&phy_rst, GPIOD_IS_IN);
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udelay(1000);
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return 0;
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}
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int dram_init(void)
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{
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return mxs_dram_init();
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}
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#ifdef CONFIG_OF_BOARD_SETUP
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static int fdt_fixup_l2switch(void *blob)
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{
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u8 ethaddr[6];
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int ret;
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if (eth_env_get_enetaddr("ethaddr", ethaddr)) {
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ret = fdt_find_and_setprop(blob,
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"/ahb@80080000/switch@800f0000",
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"local-mac-address", ethaddr, 6, 1);
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if (ret < 0)
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printf("%s: can't find usbether@1 node: %d\n",
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__func__, ret);
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}
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return 0;
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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/*
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* i.MX28 L2 switch needs manual update (fixup) of eth MAC address
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* (in 'local-mac-address' property) as it uses "switch@800f0000"
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* node, not set by default FIT image handling code in
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* "ethernet@800f0000"
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*/
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fdt_fixup_l2switch(blob);
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return 0;
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}
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#endif
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#endif /* CONFIG_SPL_BUILD */
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