u-boot/arch/riscv/cpu/fu540/spl.c
Bin Meng ffdc71bc09 Revert "riscv: cpu: fu740: clear feature disable CSR"
This reverts commit bc8bbb77f7.

This commit breaks U-Boot booting on SiFive Unleashed board, as
there is no such CSR on U54 core.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-05-14 16:26:20 +08:00

23 lines
363 B
C

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020 SiFive, Inc
* Pragnesh Patel <pragnesh.patel@sifive.com>
*/
#include <dm.h>
#include <log.h>
int spl_soc_init(void)
{
int ret;
struct udevice *dev;
/* DDR init */
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
debug("DRAM init failed: %d\n", ret);
return ret;
}
return 0;
}