mirror of
https://github.com/AsahiLinux/u-boot
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2b157d8127
The Clocking Wizard IP supports clock circuits customized to your clocking requirements. The wizard support for dynamically reconfiguring the clocking primitives for Multiply, Divide, Phase Shift/Offset, or Duty Cycle. Limited by U-Boot clk uclass without set_phase API, this patch only provides set_rate to modify the frequency. Signed-off-by: Zhengxun <zhengxunli.mxic@gmail.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
186 lines
4 KiB
C
186 lines
4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Xilinx 'Clocking Wizard' driver
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*
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* Copyright (c) 2021 Macronix Inc.
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*
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* Author: Zhengxun Li <zhengxunli@mxic.com.tw>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <div64.h>
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#include <dm/device_compat.h>
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#include <linux/iopoll.h>
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#include <linux/bitfield.h>
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#define SRR 0x0
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#define SR 0x4
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#define SR_LOCKED BIT(0)
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#define CCR(x) (0x200 + ((x) * 4))
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#define FBOUT_CFG CCR(0)
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#define FBOUT_DIV(x) (x)
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#define FBOUT_DIV_MASK GENMASK(7, 0)
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#define FBOUT_GET_DIV(x) FIELD_GET(FBOUT_DIV_MASK, x)
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#define FBOUT_MUL(x) ((x) << 8)
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#define FBOUT_MUL_MASK GENMASK(15, 8)
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#define FBOUT_GET_MUL(x) FIELD_GET(FBOUT_MUL_MASK, x)
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#define FBOUT_FRAC(x) ((x) << 16)
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#define FBOUT_FRAC_MASK GENMASK(25, 16)
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#define FBOUT_GET_FRAC(x) FIELD_GET(FBOUT_FRAC_MASK, x)
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#define FBOUT_FRAC_EN BIT(26)
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#define FBOUT_PHASE CCR(1)
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#define OUT_CFG(x) CCR(2 + ((x) * 3))
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#define OUT_DIV(x) (x)
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#define OUT_DIV_MASK GENMASK(7, 0)
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#define OUT_GET_DIV(x) FIELD_GET(OUT_DIV_MASK, x)
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#define OUT_FRAC(x) ((x) << 8)
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#define OUT_GET_MASK GENMASK(17, 8)
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#define OUT_GET_FRAC(x) FIELD_GET(OUT_GET_MASK, x)
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#define OUT_FRAC_EN BIT(18)
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#define OUT_PHASE(x) CCR(3 + ((x) * 3))
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#define OUT_DUTY(x) CCR(4 + ((x) * 3))
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#define CTRL CCR(23)
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#define CTRL_SEN BIT(2)
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#define CTRL_SADDR BIT(1)
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#define CTRL_LOAD BIT(0)
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/**
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* struct clkwzrd - Clock wizard private data structure
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*
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* @base: memory base
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* @vco_clk: voltage-controlled oscillator frequency
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*
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*/
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struct clkwzd {
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void *base;
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u64 vco_clk;
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};
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struct clkwzd_plat {
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fdt_addr_t addr;
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};
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static int clk_wzrd_enable(struct clk *clk)
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{
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struct clkwzd *priv = dev_get_priv(clk->dev);
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int ret;
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u32 val;
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ret = readl_poll_sleep_timeout(priv->base + SR, val, val & SR_LOCKED,
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1, 100);
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if (!ret) {
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writel(CTRL_SEN | CTRL_SADDR | CTRL_LOAD, priv->base + CTRL);
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writel(CTRL_SADDR, priv->base + CTRL);
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ret = readl_poll_sleep_timeout(priv->base + SR, val,
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val & SR_LOCKED, 1, 100);
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}
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return ret;
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}
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static unsigned long clk_wzrd_set_rate(struct clk *clk, ulong rate)
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{
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struct clkwzd *priv = dev_get_priv(clk->dev);
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u64 div;
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u32 cfg;
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/* Get output clock divide value */
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div = DIV_ROUND_DOWN_ULL(priv->vco_clk * 1000, rate);
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if (div < 1000 || div > 255999)
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return -EINVAL;
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cfg = OUT_DIV((u32)div / 1000);
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writel(cfg, priv->base + OUT_CFG(clk->id));
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return 0;
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}
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static struct clk_ops clk_wzrd_ops = {
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.enable = clk_wzrd_enable,
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.set_rate = clk_wzrd_set_rate,
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};
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static int clk_wzrd_probe(struct udevice *dev)
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{
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struct clkwzd_plat *plat = dev_get_plat(dev);
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struct clkwzd *priv = dev_get_priv(dev);
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struct clk clk_in1;
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u64 clock, vco_clk;
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u32 cfg;
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int ret;
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priv->base = (void *)plat->addr;
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ret = clk_get_by_name(dev, "clk_in1", &clk_in1);
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if (ret < 0) {
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dev_err(dev, "failed to get clock\n");
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return ret;
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}
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clock = clk_get_rate(&clk_in1);
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if (IS_ERR_VALUE(clock)) {
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dev_err(dev, "failed to get rate\n");
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return clock;
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}
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ret = clk_enable(&clk_in1);
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if (ret) {
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dev_err(dev, "failed to enable clock\n");
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clk_free(&clk_in1);
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return ret;
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}
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/* Read clock configuration registers */
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cfg = readl(priv->base + FBOUT_CFG);
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/* Recalculate VCO rate */
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if (cfg & FBOUT_FRAC_EN)
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vco_clk = DIV_ROUND_DOWN_ULL(clock *
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((FBOUT_GET_MUL(cfg) * 1000) +
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FBOUT_GET_FRAC(cfg)),
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1000);
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else
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vco_clk = clock * FBOUT_GET_MUL(cfg);
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priv->vco_clk = DIV_ROUND_DOWN_ULL(vco_clk, FBOUT_GET_DIV(cfg));
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return 0;
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}
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static int clk_wzrd_of_to_plat(struct udevice *dev)
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{
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struct clkwzd_plat *plat = dev_get_plat(dev);
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plat->addr = dev_read_addr(dev);
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if (plat->addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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return 0;
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}
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static const struct udevice_id clk_wzrd_ids[] = {
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{ .compatible = "xlnx,clocking-wizard" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(clk_wzrd) = {
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.name = "zynq-clk-wizard",
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.id = UCLASS_CLK,
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.of_match = clk_wzrd_ids,
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.ops = &clk_wzrd_ops,
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.probe = clk_wzrd_probe,
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.of_to_plat = clk_wzrd_of_to_plat,
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.priv_auto = sizeof(struct clkwzd),
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.plat_auto = sizeof(struct clkwzd_plat),
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};
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