mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 10:48:51 +00:00
754f8cb689
there are two boards based on da850 SOC - OMAP-L138 and AM18x. In order to differentiate between these two boards, revision id is passed to kernel via second byte of ATAG_REVISION. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
246 lines
7.4 KiB
C
246 lines
7.4 KiB
C
/*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Based on davinci_dvevm.h. Original Copyrights follow:
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* Board
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*/
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#define CONFIG_DRIVER_TI_EMAC
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#define CONFIG_USE_SPIFLASH
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/*
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* SoC Configuration
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*/
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#define CONFIG_MACH_DAVINCI_DA850_EVM
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#define CONFIG_ARM926EJS /* arm926ejs CPU core */
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#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
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#define CONFIG_SOC_DA850 /* TI DA850 SoC */
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#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
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#define CONFIG_SYS_OSCIN_FREQ 24000000
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_TEXT_BASE 0xc1080000
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#define CONFIG_DA850_AM18X_EVM
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/*
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* Memory Info
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*/
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#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
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#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
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#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
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#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
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/* memtest start addr */
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#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
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/* memtest will be run on 16MB */
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#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define CONFIG_STACKSIZE (256*1024) /* regular stack */
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/*
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* Serial Driver info
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*/
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
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#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
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#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
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#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
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#define CONFIG_BAUDRATE 115200 /* Default baud rate */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_SPI
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_WINBOND
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#define CONFIG_DAVINCI_SPI
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#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
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#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
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#define CONFIG_SF_DEFAULT_SPEED 30000000
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#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
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/*
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* I2C Configuration
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*/
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#define CONFIG_HARD_I2C
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#define CONFIG_DRIVER_DAVINCI_I2C
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#define CONFIG_SYS_I2C_SPEED 25000
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#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
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#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
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/*
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* Flash & Environment
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*/
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#ifdef CONFIG_USE_NAND
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#undef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_NAND_DAVINCI
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
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#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
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#define CONFIG_ENV_SIZE (128 << 10)
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#define CONFIG_SYS_NAND_USE_FLASH_BBT
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#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
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#define CONFIG_SYS_NAND_PAGE_2K
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#define CONFIG_SYS_NAND_CS 3
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#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
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#define CONFIG_SYS_CLE_MASK 0x10
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#define CONFIG_SYS_ALE_MASK 0x8
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#undef CONFIG_SYS_NAND_HW_ECC
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define NAND_MAX_CHIPS 1
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#endif
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/*
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* Network & Ethernet Configuration
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*/
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#ifdef CONFIG_DRIVER_TI_EMAC
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#define CONFIG_EMAC_MDIO_PHY_NUM 0
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#define CONFIG_MII
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#define CONFIG_BOOTP_DEFAULT
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_NET_RETRY_COUNT 10
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#define CONFIG_NET_MULTI
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#endif
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#ifdef CONFIG_USE_NOR
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
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#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
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#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
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#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
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#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
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#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
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#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
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+ 3)
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#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
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#endif
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#ifdef CONFIG_USE_SPIFLASH
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#undef CONFIG_ENV_IS_IN_FLASH
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#undef CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SIZE (64 << 10)
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#define CONFIG_ENV_OFFSET (256 << 10)
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#define CONFIG_ENV_SECT_SIZE (64 << 10)
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#define CONFIG_SYS_NO_FLASH
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#endif
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/*
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* U-Boot general configuration
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*/
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#define CONFIG_MISC_INIT_R
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#define CONFIG_BOOTFILE "uImage" /* Boot file name */
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#define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
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#define CONFIG_VERSION_VARIABLE
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CRC32_VERIFY
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#define CONFIG_MX_CYCLIC
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/*
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* Linux Information
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*/
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#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
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#define CONFIG_HWCONFIG /* enable hwconfig */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_BOOTARGS \
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"mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes"
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/*
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* U-Boot commands
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SAVES
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#define CONFIG_CMD_MEMORY
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#ifndef CONFIG_DRIVER_TI_EMAC
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#undef CONFIG_CMD_NET
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#undef CONFIG_CMD_DHCP
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#undef CONFIG_CMD_MII
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#undef CONFIG_CMD_PING
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#endif
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#ifdef CONFIG_USE_NAND
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#undef CONFIG_CMD_FLASH
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#undef CONFIG_CMD_IMLS
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_MTD_DEVICE
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_LZO
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#define CONFIG_RBTREE
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#define CONFIG_CMD_UBI
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#define CONFIG_CMD_UBIFS
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#endif
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#ifdef CONFIG_USE_SPIFLASH
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_FLASH
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SAVEENV
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#endif
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#if !defined(CONFIG_USE_NAND) && \
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!defined(CONFIG_USE_NOR) && \
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!defined(CONFIG_USE_SPIFLASH)
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#define CONFIG_ENV_IS_NOWHERE
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_ENV_SIZE (16 << 10)
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_ENV
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#endif
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/* additions for new relocation code, must added to all boards */
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#define CONFIG_SYS_SDRAM_BASE 0xc0000000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
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/* Fix this */ GENERATED_GBL_DATA_SIZE)
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#endif /* __CONFIG_H */
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