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https://github.com/AsahiLinux/u-boot
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6db1085623
The Gateworks imx8mp-venice-gw71xx-2x consists of a SOM + baseboard. The GW702x SOM contains the following: - i.MX8M Plus SoC - LPDDR4 memory - eMMC Boot device - Gateworks System Controller (GSC) with integrated EEPROM, button controller, and ADC's - PMIC - SOM connector providing: - eQoS GbE MII - 1x SPI - 2x I2C - 4x UART - 2x USB 3.0 - 1x PCI - 1x SDIO (4-bit 3.3V) - 1x SDIO (4-bit 3.3V/1.8V) - GPIO The GW71xx Baseboard contains the following: - 1x RJ45 GbE (eQoS from SOM) - off-board I/O connector with I2C, SPI, UART, and GPIO - Front Panel bi-color LED - re-chargeable battery (for RTC) - PCIe clock generator - 1x USB Type-C connector supporting USB 2.0 host mode with VBUS - 1x MiniPCIe socket with SIM, PCI/USB 3.0 (mux), and USB 2.0 - GPS - Accelerometer - EERPOM - Wide range DC input supply Signed-off-by: Tim Harvey <tharvey@gateworks.com>
236 lines
4.6 KiB
Text
236 lines
4.6 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2023 Gateworks Corporation
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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/ {
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led-controller {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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led-0 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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linux,default-trigger = "heartbeat";
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};
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led-1 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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};
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pcie0_refclk: pcie0-refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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pps {
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compatible = "pps-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pps>;
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gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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};
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/* off-board header */
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&ecspi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi2>;
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cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&gpio4 {
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gpio-line-names =
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"", "", "", "",
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"", "", "", "",
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"dio1", "", "", "dio0",
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"", "", "pci_usb_sel", "",
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"", "", "", "",
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"", "", "", "",
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"dio3", "", "dio2", "",
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"pci_wdis#", "", "", "";
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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accelerometer@19 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_accel>;
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compatible = "st,lis2de12";
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reg = <0x19>;
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st,drdy-int-pin = <1>;
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interrupt-parent = <&gpio4>;
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interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "INT1";
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};
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};
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&pcie_phy {
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fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
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fsl,clkreq-unsupported;
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clocks = <&pcie0_refclk>;
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clock-names = "ref";
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status = "okay";
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};
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie0>;
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reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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/* GPS */
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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/* off-board header */
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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/* USB1 Type-C front panel */
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&usb3_0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>;
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fsl,over-current-active-low;
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status = "okay";
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};
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&usb3_phy0 {
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status = "okay";
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};
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&usb_dwc3_0 {
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/* dual role is implemented but not a full featured OTG */
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adp-disable;
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hnp-disable;
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srp-disable;
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dr_mode = "otg";
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usb-role-switch;
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role-switch-default-mode = "peripheral";
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status = "okay";
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connector {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbcon1>;
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compatible = "gpio-usb-b-connector", "usb-b-connector";
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type = "micro";
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label = "Type-C";
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id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
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};
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};
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/* USB2 - MiniPCIe socket */
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&usb3_1 {
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fsl,permanently-attached;
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fsl,disable-port-power-control;
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status = "okay";
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};
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&usb3_phy1 {
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status = "okay";
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};
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&usb_dwc3_1 {
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dr_mode = "host";
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */
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MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */
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MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */
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MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000146 /* DIO2 */
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MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x40000146 /* DIO3 */
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MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */
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>;
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};
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pinctrl_accel: accelgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */
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>;
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};
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pinctrl_gpio_leds: gpioledgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */
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MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */
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>;
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};
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pinctrl_pcie0: pcie0grp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106
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>;
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};
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pinctrl_pps: ppsgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146
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>;
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};
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pinctrl_usb1: usb1grp {
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fsl,pins = <
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MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */
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>;
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};
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pinctrl_usbcon1: usbcon1grp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */
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>;
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};
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pinctrl_spi2: spi2grp {
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fsl,pins = <
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MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
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MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
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MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
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MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
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MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
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MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
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>;
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};
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};
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