mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-27 15:12:21 +00:00
25ddd1fb0a
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
369 lines
11 KiB
C
369 lines
11 KiB
C
/*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
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#define CONFIG_XM250 1 /* on a MicroSys XM250 Board */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CONFIG_SYS_TEXT_BASE 0x0
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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/*
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* Size of malloc() pool; this lives below the uppermost 128 KiB which are
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* used for the RAM copy of the uboot code
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*
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*/
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#define CONFIG_SYS_MALLOC_LEN (256*1024)
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/*
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* Hardware drivers
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*/
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#define CONFIG_NET_MULTI
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#define CONFIG_SMC91111
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#define CONFIG_SMC91111_BASE 0x04000300
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#undef CONFIG_SMC91111_EXT_PHY
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#define CONFIG_SMC_USE_32_BIT
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#undef CONFIG_SHOW_ACTIVITY
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#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
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/*
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* I2C bus
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*/
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#define CONFIG_HARD_I2C 1
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#define CONFIG_SYS_I2C_SPEED 50000
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#define CONFIG_SYS_I2C_SLAVE 0xfe
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#define CONFIG_RTC_PCF8563 1
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* A0 = 0 (hardwired) */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 4 bits = 16 octets */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* length of address */
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#define CONFIG_SYS_EEPROM_SIZE 2048 /* size in bytes */
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#undef CONFIG_SYS_I2C_INIT_BOARD /* board has no own init */
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/*
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* select serial console configuration
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*/
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#define CONFIG_PXA_SERIAL
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#define CONFIG_FFUART 1 /* we use FFUART */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_I2C
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#define CONFIG_BOOTDELAY 3
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */
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/* valid baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Definitions related to passing arguments to kernel.
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*/
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#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
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#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
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#define CONFIG_INITRD_TAG 1 /* do not send initrd params */
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#undef CONFIG_VFD /* do not send framebuffer setup */
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/*
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 4
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
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#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
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#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
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#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
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#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
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#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
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#define CONFIG_SYS_DRAM_BASE 0xa0000000
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#define CONFIG_SYS_DRAM_SIZE 0x04000000
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
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/*
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
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#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Set Lock Bit */
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Clear Lock Bits */
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#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector */
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#define CONFIG_ENV_SIZE 0x4000
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#define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
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#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */
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/******************************************************************************
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*
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* CPU specific defines
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*
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******************************************************************************/
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/*
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* GPIO settings
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*
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* GPIO pin assignments
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* GPIO Name Dir Out AF
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* 0 NC
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* 1 NC
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* 2 SIRQ1 I
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* 3 SIRQ2 I
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* 4 SIRQ3 I
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* 5 DMAACK1 O 0
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* 6 DMAACK2 O 0
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* 7 DMAACK3 O 0
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* 8 TC1 O 0
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* 9 TC2 O 0
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* 10 TC3 O 0
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* 11 nDMAEN O 1
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* 12 AENCTRL O 0
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* 13 PLDTC O 0
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* 14 ETHIRQ I
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* 15 NC
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* 16 NC
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* 17 NC
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* 18 RDY I
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* 19 DMASIO I
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* 20 ETHIRQ NC
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* 21 NC
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* 22 PGMEN O 1 FIXME for debug only enable flash
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* 23 NC
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* 24 NC
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* 25 NC
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* 26 NC
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* 27 NC
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* 28 NC
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* 29 NC
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* 30 NC
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* 31 NC
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* 32 NC
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* 33 NC
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* 34 FFRXD I 01
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* 35 FFCTS I 01
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* 36 FFDCD I 01
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* 37 FFDSR I 01
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* 38 FFRI I 01
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* 39 FFTXD O 1 10
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* 40 FFDTR O 0 10
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* 41 FFRTS O 0 10
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* 42 RS232FOFF O 0 00
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* 43 NC
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* 44 NC
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* 45 IRSL0 O 0
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* 46 IRRX0 I 01
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* 47 IRTX0 O 0 10
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* 48 NC
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* 49 nIOWE O 0
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* 50 NC
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* 51 NC
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* 52 NC
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* 53 NC
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* 54 NC
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* 55 NC
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* 56 NC
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* 57 NC
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* 58 DKDIRQ I
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* 59 NC
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* 60 NC
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* 61 NC
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* 62 NC
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* 63 NC
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* 64 COMLED O 0
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* 65 COMLED O 0
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* 66 COMLED O 0
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* 67 COMLED O 0
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* 68 COMLED O 0
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* 69 COMLED O 0
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* 70 COMLED O 0
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* 71 COMLED O 0
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* 72 NC
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* 73 NC
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* 74 NC
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* 75 NC
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* 76 NC
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* 77 NC
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* 78 CSIO O 1
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* 79 NC
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* 80 CSETH O 1
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*
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* NOTE: All NC's are defined to be outputs
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*
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*/
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/* Pin direction control */
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#define CONFIG_SYS_GPDR0_VAL 0xd3808000
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#define CONFIG_SYS_GPDR1_VAL 0xfcffab83
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#define CONFIG_SYS_GPDR2_VAL 0x0001ffff
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/* Set and Clear registers */
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#define CONFIG_SYS_GPSR0_VAL 0x00008000
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#define CONFIG_SYS_GPSR1_VAL 0x00ff0002
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#define CONFIG_SYS_GPSR2_VAL 0x0001c000
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#define CONFIG_SYS_GPCR0_VAL 0x00000000
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#define CONFIG_SYS_GPCR1_VAL 0x00000000
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#define CONFIG_SYS_GPCR2_VAL 0x00000000
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/* Edge detect registers (these are set by the kernel) */
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#define CONFIG_SYS_GRER0_VAL 0x00002180
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#define CONFIG_SYS_GRER1_VAL 0x00000000
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#define CONFIG_SYS_GRER2_VAL 0x00000000
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#define CONFIG_SYS_GFER0_VAL 0x000043e0
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#define CONFIG_SYS_GFER1_VAL 0x00000000
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#define CONFIG_SYS_GFER2_VAL 0x00000000
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/* Alternate function registers */
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#define CONFIG_SYS_GAFR0_L_VAL 0x80000004
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#define CONFIG_SYS_GAFR0_U_VAL 0x595a8010
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#define CONFIG_SYS_GAFR1_L_VAL 0x699a9559
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#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aaaa
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#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
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#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
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/*
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* Clocks, power control and interrupts
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*/
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#define CONFIG_SYS_PSSR_VAL 0x00000030
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#define CONFIG_SYS_CCCR 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */
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#define CONFIG_SYS_CKEN 0x000141ec /* FFUART and STUART enabled */
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#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
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/* FIXME
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*
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* RTC settings
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* Watchdog
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*
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*/
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/*
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* Memory settings
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*
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*/
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#define CONFIG_SYS_MSC0_VAL 0x122423f0 /* FLASH / LAN (cs0)/(cS1) */
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#define CONFIG_SYS_MSC1_VAL 0x35f4aa4c /* USB / ST3+ST5 (cs2)/(cS3) */
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#define CONFIG_SYS_MSC2_VAL 0x35f435fc /* IDE / BCR + WatchDog (cs4)/(cS5) */
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#define CONFIG_SYS_MDCNFG_VAL 0x000009c9
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#define CONFIG_SYS_MDMRS_VAL 0x00220022
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#define CONFIG_SYS_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in lowlevel_init.S */
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#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
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#define CONFIG_SYS_SXCNFG_VAL 0x00000000
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/*
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* PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
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*/
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#define CONFIG_SYS_MECR_VAL 0x00000000
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#define CONFIG_SYS_MCMEM0_VAL 0x00010504
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#define CONFIG_SYS_MCMEM1_VAL 0x00010504
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#define CONFIG_SYS_MCATT0_VAL 0x00010504
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#define CONFIG_SYS_MCATT1_VAL 0x00010504
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#define CONFIG_SYS_MCIO0_VAL 0x00004715
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#define CONFIG_SYS_MCIO1_VAL 0x00004715
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/* Board specific defines */
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#ifndef __ASSEMBLY__
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/* global prototypes */
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void led_code(int code, int color);
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#endif
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#endif /* __CONFIG_H */
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