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94c30f9c8f
As explained in commit 3bedbcc3aa ("arm: mvebu: a38x: serdes: Don't
overwrite read-only SAR PCIe registers") it is required to set Maximum Link
Width bits of PCIe Root Port Link Capabilities Register depending of number
of used serdes lanes. As this register is part of PCIe address space and
not serdes address space, move it into pci_mvebu.c driver.
Read number of PCIe lanes from DT property "num-lanes" which is used also
by other PCIe controller drivers in Linux kernel. If this property is
absent then it defaults to 1. This property needs to be set to 4 for every
mvebu board which use PEX_ROOT_COMPLEX_X4 or PEX_BUS_MODE_X4.
Enabling of PCIe port needs to be done afer all registers in PCIe address
space are properly configure. For this purpose use new mvebu-reset driver
(part of system-controller) and remove this code from serdes code.
Because some PCIe ports cannot be enabled individually, it is required to
first setup all PCIe ports and then enable them.
This change contains also all required "num-lanes" and "resets" DTS
properties, to make pci_mvebu.c driver work correctly.
Signed-off-by: Pali Rohár <pali@kernel.org>
6 lines
218 B
Makefile
6 lines
218 B
Makefile
# SPDX-License-Identifier: GPL-2.0+
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obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec.o
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obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec-38x.o
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obj-$(CONFIG_SPL_BUILD) += seq_exec.o
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obj-$(CONFIG_SPL_BUILD) += sys_env_lib.o
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