mirror of
https://github.com/AsahiLinux/u-boot
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f3285deeca
Since commit [1] A53 u-boot proper is broken.
This is because nodes marked as 'bootph-pre-ram' are
not available at u-boot proper before relocation.
To fix this we mark all nodes in sk-u-boot.dtsi as
'bootph-all'.
Move cbass_mcu node to -r5-sk.dts as it is only required
for R5 SPL.
[1]
9e644284ab ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
105 lines
2.2 KiB
Text
105 lines
2.2 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include "k3-am642-sk.dts"
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#include "k3-am64-sk-lp4-1600MTs.dtsi"
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#include "k3-am64-ddr.dtsi"
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#include "k3-am642-sk-u-boot.dtsi"
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/ {
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aliases {
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remoteproc0 = &sysctrler;
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remoteproc1 = &a53_0;
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};
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a53_0: a53@0 {
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compatible = "ti,am654-rproc";
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reg = <0x00 0x00a90000 0x00 0x10>;
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power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
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<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
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<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
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resets = <&k3_reset 135 0>;
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clocks = <&k3_clks 61 0>;
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assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
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assigned-clock-parents = <&k3_clks 61 2>;
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assigned-clock-rates = <200000000>, <1000000000>;
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ti,sci = <&dmsc>;
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ti,sci-proc-id = <32>;
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ti,sci-host-id = <10>;
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bootph-pre-ram;
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};
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clk_200mhz: dummy-clock-200mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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bootph-pre-ram;
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};
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};
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&cbass_main {
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sysctrler: sysctrler {
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compatible = "ti,am654-system-controller";
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mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
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mbox-names = "tx", "rx";
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bootph-pre-ram;
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};
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};
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&main_esm {
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bootph-pre-ram;
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};
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&cbass_mcu {
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bootph-pre-ram;
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};
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&mcu_esm {
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bootph-pre-ram;
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};
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&dmsc {
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mboxes= <&secure_proxy_main 0>,
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<&secure_proxy_main 1>,
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<&secure_proxy_main 0>;
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mbox-names = "rx", "tx", "notify";
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ti,host-id = <35>;
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ti,secure-host;
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};
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&sdhci1 {
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clocks = <&clk_200mhz>;
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clock-names = "clk_xin";
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};
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&serdes_wiz0 {
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status = "okay";
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};
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/* UART is initialized before SYSFW is started
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* so we can't do any power-domain/clock operations.
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* Delete clock/power-domain properties to avoid
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* UART init failure
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*/
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&main_uart0 {
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/delete-property/ power-domains;
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/delete-property/ clocks;
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/delete-property/ clock-names;
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};
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/* timer init is called as part of rproc_start() while
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* starting System Firmware, so any clock/power-domain
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* operations will fail as SYSFW is not yet up and running.
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* Delete all clock/power-domain properties to avoid
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* timer init failure.
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* This is an always on timer at 20MHz.
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*/
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&main_timer0 {
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/delete-property/ clocks;
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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/delete-property/ power-domains;
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};
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