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https://github.com/AsahiLinux/u-boot
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170 lines
4.1 KiB
ArmAsm
170 lines
4.1 KiB
ArmAsm
/*
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* (C) Copyright 2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include "test_burst.h"
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.text
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/*
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* void mmu_init(void);
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*
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* This function turns the MMU on
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*
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* Three 8 MByte regions are mapped 1:1, uncached
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* - SDRAM lower 8 MByte
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* - SDRAM higher 8 MByte
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* - IMMR
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*/
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.global mmu_init
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mmu_init:
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tlbia /* Invalidate all TLB entries */
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li r8, 0
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mtspr MI_CTR, r8 /* Set instruction control to zero */
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lis r8, MD_RESETVAL@h
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mtspr MD_CTR, r8 /* Set data TLB control */
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/* Now map the lower 8 Meg into the TLBs. For this quick hack,
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* we can load the instruction and data TLB registers with the
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* same values.
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*/
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li r8, MI_EVALID /* Create EPN for address 0 */
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mtspr MI_EPN, r8
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mtspr MD_EPN, r8
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li r8, MI_PS8MEG /* Set 8M byte page */
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ori r8, r8, MI_SVALID /* Make it valid */
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mtspr MI_TWC, r8
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mtspr MD_TWC, r8
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li r8, MI_BOOTINIT|0x2 /* Create RPN for address 0 */
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mtspr MI_RPN, r8 /* Store TLB entry */
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mtspr MD_RPN, r8
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lis r8, MI_Kp@h /* Set the protection mode */
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mtspr MI_AP, r8
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mtspr MD_AP, r8
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/* Now map the higher 8 Meg into the TLBs. For this quick hack,
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* we can load the instruction and data TLB registers with the
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* same values.
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*/
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lwz r9,20(r29) /* gd->ram_size */
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addis r9,r9,-0x80
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mr r8, r9 /* Higher 8 Meg in SDRAM */
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ori r8, r8, MI_EVALID /* Mark page valid */
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mtspr MI_EPN, r8
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mtspr MD_EPN, r8
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li r8, MI_PS8MEG /* Set 8M byte page */
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ori r8, r8, MI_SVALID /* Make it valid */
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mtspr MI_TWC, r8
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mtspr MD_TWC, r8
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mr r8, r9
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ori r8, r8, MI_BOOTINIT|0x2
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mtspr MI_RPN, r8 /* Store TLB entry */
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mtspr MD_RPN, r8
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lis r8, MI_Kp@h /* Set the protection mode */
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mtspr MI_AP, r8
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mtspr MD_AP, r8
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/* Map another 8 MByte at the IMMR to get the processor
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* internal registers (among other things).
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*/
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mfspr r9, 638 /* Get current IMMR */
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andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
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mr r8, r9 /* Create vaddr for TLB */
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ori r8, r8, MD_EVALID /* Mark it valid */
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mtspr MD_EPN, r8
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li r8, MD_PS8MEG /* Set 8M byte page */
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ori r8, r8, MD_SVALID /* Make it valid */
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mtspr MD_TWC, r8
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mr r8, r9 /* Create paddr for TLB */
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ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
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mtspr MD_RPN, r8
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/* We now have the lower and higher 8 Meg mapped into TLB entries,
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* and the caches ready to work.
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*/
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mfmsr r0
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ori r0,r0,MSR_DR|MSR_IR
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mtspr SRR1,r0
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mflr r0
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mtspr SRR0,r0
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SYNC
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rfi /* enables MMU */
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/*
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* void caches_init(void);
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*/
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.globl caches_init
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caches_init:
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sync
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mfspr r3, IC_CST /* Clear error bits */
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mfspr r3, DC_CST
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lis r3, IDC_UNALL@h /* Unlock all */
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mtspr IC_CST, r3
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mtspr DC_CST, r3
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lis r3, IDC_INVALL@h /* Invalidate all */
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mtspr IC_CST, r3
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mtspr DC_CST, r3
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lis r3, IDC_ENABLE@h /* Enable all */
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mtspr IC_CST, r3
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mtspr DC_CST, r3
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blr
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/*
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* void flush_dcache_range(unsigned long start, unsigned long stop);
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*/
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.global flush_dcache_range
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flush_dcache_range:
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li r5,CACHE_LINE_SIZE-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,LG_CACHE_LINE_SIZE
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beqlr
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mtctr r4
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1: dcbf 0,r3
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addi r3,r3,CACHE_LINE_SIZE
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bdnz 1b
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sync /* wait for dcbf's to get to ram */
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blr
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/*
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* void disable_interrupts(void);
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*/
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.global disable_interrupts
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disable_interrupts:
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mfmsr r0
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rlwinm r0,r0,0,17,15
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mtmsr r0
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blr
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