u-boot/drivers/clk/uniphier
Masahiro Yamada 94bf34b172 clk: uniphier: add NAND 200MHz clock
The Denali NAND controller IP needs three clocks:

 - clk: controller core clock

 - clk_x: bus interface clock

 - ecc_clk: clock at which ECC circuitry is run

Currently, only the first one (50MHz) is provided.  The rest of the
two clock ports must be connected to the 200MHz clock line.  Add this.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-29 11:38:38 +09:00
..
clk-uniphier-core.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
clk-uniphier-mio.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
clk-uniphier-sys.c clk: uniphier: add NAND 200MHz clock 2018-12-29 11:38:38 +09:00
clk-uniphier.h SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
Kconfig clk: uniphier: disable SPL_CLK 2018-04-24 00:35:35 +09:00
Makefile clk: uniphier: add System clock support 2017-08-30 09:07:04 +09:00