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The ICH SPI controller supports two variants, one of which is ICH7 compatible and the other is ICH9 compatible. Change 'pch_version' to 'ich_version' to better match its original name. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Simon Glass <sjg@chromium.org>
161 lines
3 KiB
C
161 lines
3 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* This file is derived from the flashrom project.
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*/
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#ifndef _ICH_H_
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#define _ICH_H_
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struct ich7_spi_regs {
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uint16_t spis;
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uint16_t spic;
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uint32_t spia;
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uint64_t spid[8];
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uint64_t _pad;
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uint32_t bbar;
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uint16_t preop;
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uint16_t optype;
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uint8_t opmenu[8];
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} __packed;
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struct ich9_spi_regs {
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uint32_t bfpr; /* 0x00 */
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uint16_t hsfs;
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uint16_t hsfc;
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uint32_t faddr;
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uint32_t _reserved0;
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uint32_t fdata[16]; /* 0x10 */
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uint32_t frap; /* 0x50 */
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uint32_t freg[5];
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uint32_t _reserved1[3];
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uint32_t pr[5]; /* 0x74 */
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uint32_t _reserved2[2];
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uint8_t ssfs; /* 0x90 */
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uint8_t ssfc[3];
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uint16_t preop; /* 0x94 */
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uint16_t optype;
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uint8_t opmenu[8]; /* 0x98 */
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uint32_t bbar;
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uint8_t _reserved3[12];
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uint32_t fdoc; /* 0xb0 */
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uint32_t fdod;
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uint8_t _reserved4[8];
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uint32_t afc; /* 0xc0 */
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uint32_t lvscc;
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uint32_t uvscc;
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uint8_t _reserved5[4];
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uint32_t fpb; /* 0xd0 */
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uint8_t _reserved6[28];
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uint32_t srdl; /* 0xf0 */
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uint32_t srdc;
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uint32_t scs;
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uint32_t bcr;
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} __packed;
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enum {
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SPIS_SCIP = 0x0001,
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SPIS_GRANT = 0x0002,
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SPIS_CDS = 0x0004,
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SPIS_FCERR = 0x0008,
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SSFS_AEL = 0x0010,
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SPIS_LOCK = 0x8000,
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SPIS_RESERVED_MASK = 0x7ff0,
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SSFS_RESERVED_MASK = 0x7fe2
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};
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enum {
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SPIC_SCGO = 0x000002,
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SPIC_ACS = 0x000004,
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SPIC_SPOP = 0x000008,
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SPIC_DBC = 0x003f00,
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SPIC_DS = 0x004000,
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SPIC_SME = 0x008000,
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SSFC_SCF_MASK = 0x070000,
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SSFC_RESERVED = 0xf80000,
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/* Mask for speed byte, biuts 23:16 of SSFC */
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SSFC_SCF_33MHZ = 0x01,
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};
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enum {
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HSFS_FDONE = 0x0001,
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HSFS_FCERR = 0x0002,
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HSFS_AEL = 0x0004,
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HSFS_BERASE_MASK = 0x0018,
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HSFS_BERASE_SHIFT = 3,
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HSFS_SCIP = 0x0020,
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HSFS_FDOPSS = 0x2000,
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HSFS_FDV = 0x4000,
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HSFS_FLOCKDN = 0x8000
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};
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enum {
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HSFC_FGO = 0x0001,
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HSFC_FCYCLE_MASK = 0x0006,
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HSFC_FCYCLE_SHIFT = 1,
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HSFC_FDBC_MASK = 0x3f00,
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HSFC_FDBC_SHIFT = 8,
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HSFC_FSMIE = 0x8000
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};
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enum {
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SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0,
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SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1,
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SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2,
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SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3
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};
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enum {
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ICH_MAX_CMD_LEN = 5,
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};
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struct spi_trans {
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uint8_t cmd[ICH_MAX_CMD_LEN];
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int cmd_len;
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const uint8_t *out;
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uint32_t bytesout;
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uint8_t *in;
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uint32_t bytesin;
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uint8_t type;
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uint8_t opcode;
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uint32_t offset;
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};
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#define SPI_OPCODE_WREN 0x06
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#define SPI_OPCODE_FAST_READ 0x0b
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enum ich_version {
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ICHV_7,
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ICHV_9,
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};
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struct ich_spi_platdata {
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enum ich_version ich_version; /* Controller version, 7 or 9 */
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};
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struct ich_spi_priv {
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int ichspi_lock;
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int locked;
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int opmenu;
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int menubytes;
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void *base; /* Base of register set */
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int preop;
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int optype;
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int addr;
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int data;
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unsigned databytes;
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int status;
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int control;
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int bbar;
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int bcr;
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uint32_t *pr; /* only for ich9 */
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int speed; /* pointer to speed control */
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ulong max_speed; /* Maximum bus speed in MHz */
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ulong cur_speed; /* Current bus speed */
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struct spi_trans trans; /* current transaction in progress */
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};
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#endif /* _ICH_H_ */
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