mirror of
https://github.com/AsahiLinux/u-boot
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a4814a69d3
commit 0edf8b5b2f breaks
building on a different directory with the O= parameter.
The patch wil fix this issue, generating always asm-offsets.h before
the other targets.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Matthias Weisser <weisserm@arcor.de>
CC: Wolfgang Denk <wd@denx.de>
110 lines
2.6 KiB
ArmAsm
110 lines
2.6 KiB
ArmAsm
/*
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* (C) Copyright 2011
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* Matthias Weisser <weisserm@arcor.de>
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*
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* (C) Copyright 2009 DENX Software Engineering
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* Author: John Rigby <jrigby@gmail.com>
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*
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* Based on U-Boot and RedBoot sources for several different i.mx
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* platforms.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/macro.h>
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#include <asm/arch/macro.h>
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#include <asm/arch/imx-regs.h>
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#include <generated/asm-offsets.h>
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/*
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* clocks
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*/
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.macro init_clocks
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/* disable clock output */
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write32 IMX_CCM_BASE + CCM_MCR, 0x00000000
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write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000
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/*
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* enable all implemented clocks in all three
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* clock control registers
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*/
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write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
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write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
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write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff
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/* Devide NAND clock by 32 */
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write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
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.endm
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/*
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* sdram controller init
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*/
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.macro init_lpddr
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ldr r0, =IMX_ESDRAMC_BASE
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ldr r2, =IMX_SDRAM_BANK0_BASE
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/*
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* reset SDRAM controller
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* then wait for initialization to complete
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*/
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ldr r1, =(1 << 1) | (1 << 2)
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str r1, [r0, #ESDRAMC_ESDMISC]
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1: ldr r3, [r0, #ESDRAMC_ESDMISC]
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tst r3, #(1 << 31)
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beq 1b
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ldr r1, =(1 << 2)
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str r1, [r0, #ESDRAMC_ESDMISC]
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ldr r1, =0x002a7420
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str r1, [r0, #ESDRAMC_ESDCFG0]
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/* control | precharge */
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ldr r1, =0x92216008
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str r1, [r0, #ESDRAMC_ESDCTL0]
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/* dram command encoded in address */
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str r1, [r2, #0x400]
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/* auto refresh */
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ldr r1, =0xa2216008
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str r1, [r0, #ESDRAMC_ESDCTL0]
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/* read dram twice to auto refresh */
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ldr r3, [r2]
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ldr r3, [r2]
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/* control | load mode */
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ldr r1, =0xb2216008
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str r1, [r0, #ESDRAMC_ESDCTL0]
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/* mode register of lpddram */
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strb r1, [r2, #0x33]
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/* extended mode register of lpddrram */
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ldr r2, =0x81000000
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strb r1, [r2]
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/* control | normal */
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ldr r1, =0x82216008
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str r1, [r0, #ESDRAMC_ESDCTL0]
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.endm
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.globl lowlevel_init
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lowlevel_init:
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init_aips
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init_max
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init_clocks
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init_lpddr
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mov pc, lr
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