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66fd3d1ce7
(includes support for Intel 82365 and compatible PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers)
234 lines
7.9 KiB
C
234 lines
7.9 KiB
C
/*
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* ti113x.h 1.31 2002/05/12 18:19:47
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*
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* The contents of this file are subject to the Mozilla Public License
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* Version 1.1 (the "License"); you may not use this file except in
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* compliance with the License. You may obtain a copy of the License
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* at http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS"
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* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
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* the License for the specific language governing rights and
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* limitations under the License.
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*
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* The initial developer of the original code is David A. Hinds
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* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
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* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
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*
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* Alternatively, the contents of this file may be used under the
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* terms of the GNU General Public License version 2 (the "GPL"), in
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* which case the provisions of the GPL are applicable instead of the
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* above. If you wish to allow the use of your version of this file
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* only under the terms of the GPL and not to allow others to use
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* your version of this file under the MPL, indicate your decision by
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* deleting the provisions above and replace them with the notice and
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* other provisions required by the GPL. If you do not delete the
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* provisions above, a recipient may use your version of this file
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* under either the MPL or the GPL.
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*/
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#ifndef _LINUX_TI113X_H
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#define _LINUX_TI113X_H
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#ifndef PCI_VENDOR_ID_TI
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#define PCI_VENDOR_ID_TI 0x104c
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#endif
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#ifndef PCI_DEVICE_ID_TI_1130
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#define PCI_DEVICE_ID_TI_1130 0xac12
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#endif
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#ifndef PCI_DEVICE_ID_TI_1031
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#define PCI_DEVICE_ID_TI_1031 0xac13
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#endif
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#ifndef PCI_DEVICE_ID_TI_1131
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#define PCI_DEVICE_ID_TI_1131 0xac15
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#endif
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#ifndef PCI_DEVICE_ID_TI_1210
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#define PCI_DEVICE_ID_TI_1210 0xac1a
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#endif
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#ifndef PCI_DEVICE_ID_TI_1211
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#define PCI_DEVICE_ID_TI_1211 0xac1e
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#endif
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#ifndef PCI_DEVICE_ID_TI_1220
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#define PCI_DEVICE_ID_TI_1220 0xac17
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#endif
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#ifndef PCI_DEVICE_ID_TI_1221
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#define PCI_DEVICE_ID_TI_1221 0xac19
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#endif
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#ifndef PCI_DEVICE_ID_TI_1250A
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#define PCI_DEVICE_ID_TI_1250A 0xac16
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#endif
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#ifndef PCI_DEVICE_ID_TI_1225
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#define PCI_DEVICE_ID_TI_1225 0xac1c
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#endif
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#ifndef PCI_DEVICE_ID_TI_1251A
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#define PCI_DEVICE_ID_TI_1251A 0xac1d
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#endif
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#ifndef PCI_DEVICE_ID_TI_1251B
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#define PCI_DEVICE_ID_TI_1251B 0xac1f
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#endif
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#ifndef PCI_DEVICE_ID_TI_1410
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#define PCI_DEVICE_ID_TI_1410 0xac50
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#endif
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#ifndef PCI_DEVICE_ID_TI_1420
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#define PCI_DEVICE_ID_TI_1420 0xac51
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#endif
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#ifndef PCI_DEVICE_ID_TI_1450
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#define PCI_DEVICE_ID_TI_1450 0xac1b
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#endif
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#ifndef PCI_DEVICE_ID_TI_1451
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#define PCI_DEVICE_ID_TI_1451 0xac52
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#endif
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#ifndef PCI_DEVICE_ID_TI_1510
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#define PCI_DEVICE_ID_TI_1510 0xac56
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#endif
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#ifndef PCI_DEVICE_ID_TI_4410
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#define PCI_DEVICE_ID_TI_4410 0xac41
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#endif
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#ifndef PCI_DEVICE_ID_TI_4450
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#define PCI_DEVICE_ID_TI_4450 0xac40
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#endif
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#ifndef PCI_DEVICE_ID_TI_4451
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#define PCI_DEVICE_ID_TI_4451 0xac42
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#endif
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/* Register definitions for TI 113X PCI-to-CardBus bridges */
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/* System Control Register */
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#define TI113X_SYSTEM_CONTROL 0x80 /* 32 bit */
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#define TI113X_SCR_SMIROUTE 0x04000000
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#define TI113X_SCR_SMISTATUS 0x02000000
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#define TI113X_SCR_SMIENB 0x01000000
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#define TI113X_SCR_VCCPROT 0x00200000
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#define TI113X_SCR_REDUCEZV 0x00100000
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#define TI113X_SCR_CDREQEN 0x00080000
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#define TI113X_SCR_CDMACHAN 0x00070000
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#define TI113X_SCR_SOCACTIVE 0x00002000
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#define TI113X_SCR_PWRSTREAM 0x00000800
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#define TI113X_SCR_DELAYUP 0x00000400
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#define TI113X_SCR_DELAYDOWN 0x00000200
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#define TI113X_SCR_INTERROGATE 0x00000100
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#define TI113X_SCR_CLKRUN_SEL 0x00000080
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#define TI113X_SCR_PWRSAVINGS 0x00000040
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#define TI113X_SCR_SUBSYSRW 0x00000020
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#define TI113X_SCR_CB_DPAR 0x00000010
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#define TI113X_SCR_CDMA_EN 0x00000008
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#define TI113X_SCR_ASYNC_IRQ 0x00000004
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#define TI113X_SCR_KEEPCLK 0x00000002
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#define TI113X_SCR_CLKRUN_ENA 0x00000001
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#define TI122X_SCR_SER_STEP 0xc0000000
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#define TI122X_SCR_INTRTIE 0x20000000
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#define TI122X_SCR_P2CCLK 0x08000000
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#define TI122X_SCR_CBRSVD 0x00400000
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#define TI122X_SCR_MRBURSTDN 0x00008000
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#define TI122X_SCR_MRBURSTUP 0x00004000
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#define TI122X_SCR_RIMUX 0x00000001
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/* Multimedia Control Register */
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#define TI1250_MULTIMEDIA_CTL 0x84 /* 8 bit */
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#define TI1250_MMC_ZVOUTEN 0x80
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#define TI1250_MMC_PORTSEL 0x40
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#define TI1250_MMC_ZVEN1 0x02
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#define TI1250_MMC_ZVEN0 0x01
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#define TI1250_GENERAL_STATUS 0x85 /* 8 bit */
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#define TI1250_GPIO0_CONTROL 0x88 /* 8 bit */
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#define TI1250_GPIO1_CONTROL 0x89 /* 8 bit */
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#define TI1250_GPIO2_CONTROL 0x8a /* 8 bit */
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#define TI1250_GPIO3_CONTROL 0x8b /* 8 bit */
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#define TI12XX_IRQMUX 0x8c /* 32 bit */
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/* Retry Status Register */
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#define TI113X_RETRY_STATUS 0x90 /* 8 bit */
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#define TI113X_RSR_PCIRETRY 0x80
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#define TI113X_RSR_CBRETRY 0x40
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#define TI113X_RSR_TEXP_CBB 0x20
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#define TI113X_RSR_MEXP_CBB 0x10
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#define TI113X_RSR_TEXP_CBA 0x08
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#define TI113X_RSR_MEXP_CBA 0x04
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#define TI113X_RSR_TEXP_PCI 0x02
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#define TI113X_RSR_MEXP_PCI 0x01
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/* Card Control Register */
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#define TI113X_CARD_CONTROL 0x91 /* 8 bit */
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#define TI113X_CCR_RIENB 0x80
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#define TI113X_CCR_ZVENABLE 0x40
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#define TI113X_CCR_PCI_IRQ_ENA 0x20
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#define TI113X_CCR_PCI_IREQ 0x10
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#define TI113X_CCR_PCI_CSC 0x08
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#define TI113X_CCR_SPKROUTEN 0x02
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#define TI113X_CCR_IFG 0x01
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#define TI1220_CCR_PORT_SEL 0x20
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#define TI122X_CCR_AUD2MUX 0x04
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/* Device Control Register */
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#define TI113X_DEVICE_CONTROL 0x92 /* 8 bit */
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#define TI113X_DCR_5V_FORCE 0x40
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#define TI113X_DCR_3V_FORCE 0x20
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#define TI113X_DCR_IMODE_MASK 0x06
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#define TI113X_DCR_IMODE_ISA 0x02
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#define TI113X_DCR_IMODE_SERIAL 0x04
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#define TI12XX_DCR_IMODE_PCI_ONLY 0x00
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#define TI12XX_DCR_IMODE_ALL_SERIAL 0x06
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/* Buffer Control Register */
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#define TI113X_BUFFER_CONTROL 0x93 /* 8 bit */
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#define TI113X_BCR_CB_READ_DEPTH 0x08
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#define TI113X_BCR_CB_WRITE_DEPTH 0x04
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#define TI113X_BCR_PCI_READ_DEPTH 0x02
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#define TI113X_BCR_PCI_WRITE_DEPTH 0x01
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/* Diagnostic Register */
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#define TI1250_DIAGNOSTIC 0x93 /* 8 bit */
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#define TI1250_DIAG_TRUE_VALUE 0x80
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#define TI1250_DIAG_PCI_IREQ 0x40
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#define TI1250_DIAG_PCI_CSC 0x20
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#define TI1250_DIAG_ASYNC_CSC 0x01
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/* DMA Registers */
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#define TI113X_DMA_0 0x94 /* 32 bit */
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#define TI113X_DMA_1 0x98 /* 32 bit */
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/* ExCA IO offset registers */
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#define TI113X_IO_OFFSET(map) (0x36+((map)<<1))
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/* Data structure for tracking vendor-specific state */
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typedef struct ti113x_state_t {
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u32 sysctl; /* TI113X_SYSTEM_CONTROL */
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u8 cardctl; /* TI113X_CARD_CONTROL */
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u8 devctl; /* TI113X_DEVICE_CONTROL */
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u8 diag; /* TI1250_DIAGNOSTIC */
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u32 irqmux; /* TI12XX_IRQMUX */
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} ti113x_state_t;
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#define TI_PCIC_ID \
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IS_TI1130, IS_TI1131, IS_TI1031, IS_TI1210, IS_TI1211, \
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IS_TI1220, IS_TI1221, IS_TI1225, IS_TI1250A, IS_TI1251A, \
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IS_TI1251B, IS_TI1410, IS_TI1420, IS_TI1450, IS_TI1451, \
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IS_TI1510, IS_TI4410, IS_TI4450, IS_TI4451
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#define TI_PCIC_INFO \
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{ "TI 1130", IS_TI|IS_CARDBUS, ID(TI, 1130) }, \
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{ "TI 1131", IS_TI|IS_CARDBUS, ID(TI, 1131) }, \
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{ "TI 1031", IS_TI|IS_CARDBUS, ID(TI, 1031) }, \
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{ "TI 1210", IS_TI|IS_CARDBUS, ID(TI, 1210) }, \
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{ "TI 1211", IS_TI|IS_CARDBUS, ID(TI, 1211) }, \
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{ "TI 1220", IS_TI|IS_CARDBUS, ID(TI, 1220) }, \
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{ "TI 1221", IS_TI|IS_CARDBUS, ID(TI, 1221) }, \
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{ "TI 1225", IS_TI|IS_CARDBUS, ID(TI, 1225) }, \
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{ "TI 1250A", IS_TI|IS_CARDBUS, ID(TI, 1250A) }, \
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{ "TI 1251A", IS_TI|IS_CARDBUS, ID(TI, 1251A) }, \
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{ "TI 1251B", IS_TI|IS_CARDBUS, ID(TI, 1251B) }, \
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{ "TI 1410", IS_TI|IS_CARDBUS, ID(TI, 1410) }, \
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{ "TI 1420", IS_TI|IS_CARDBUS, ID(TI, 1420) }, \
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{ "TI 1450", IS_TI|IS_CARDBUS, ID(TI, 1450) }, \
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{ "TI 1451", IS_TI|IS_CARDBUS, ID(TI, 1451) }, \
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{ "TI 1510", IS_TI|IS_CARDBUS, ID(TI, 1510) }, \
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{ "TI 4410", IS_TI|IS_CARDBUS, ID(TI, 4410) }, \
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{ "TI 4450", IS_TI|IS_CARDBUS, ID(TI, 4450) }, \
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{ "TI 4451", IS_TI|IS_CARDBUS, ID(TI, 4451) }
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#endif /* _LINUX_TI113X_H */
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