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https://github.com/AsahiLinux/u-boot
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f3543e6944
This is not needed and we should avoid typedefs. Use the struct instead and rename it to indicate that it really is a legacy struct. Signed-off-by: Simon Glass <sjg@chromium.org>
144 lines
3.7 KiB
C
144 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 MediaTek Inc. All rights reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <image.h>
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#include <asm/system.h>
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#include <asm/sections.h>
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#include <asm/cacheops.h>
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#include <asm/mipsregs.h>
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#include <asm/cm.h>
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#define INDEX_STORE_DATA_SD 0x0f
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typedef void __noreturn (*image_entry_noargs_t)(void);
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/*
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* Lock L2 cache and fill data
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* Assume that data is 4-byte aligned and start_addr/size is 32-byte aligned
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*/
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static void fill_lock_l2cache(uintptr_t dataptr, ulong start_addr, ulong size)
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{
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ulong slsize = CONFIG_SYS_DCACHE_LINE_SIZE;
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ulong end_addr = start_addr + size;
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const u32 *data = (u32 *)dataptr;
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ulong i, addr;
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u32 val;
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/* Clear WSC & SPR bit in ErrCtl */
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val = read_c0_ecc();
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val &= 0xcfffffff;
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write_c0_ecc(val);
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execution_hazard_barrier();
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for (addr = start_addr; addr < end_addr; addr += slsize) {
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/* Set STagLo to lock cache line */
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write_c0_staglo((addr & 0x1ffff800) | 0xa0);
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mips_cache(INDEX_STORE_TAG_SD, (void *)addr);
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/* Fill data */
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for (i = 0; i < slsize; i += 8) {
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val = *data++;
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__write_32bit_c0_register($28, 5, val); /* sdtaglo */
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val = *data++;
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__write_32bit_c0_register($29, 5, val); /* sdtaghi */
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mips_cache(INDEX_STORE_DATA_SD, (void *)(addr + i));
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}
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}
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sync();
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}
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/* A simple function to initialize MT7621's cache */
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static void mt7621_cache_init(void)
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{
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void __iomem *cm_base = (void *)KSEG1ADDR(CONFIG_MIPS_CM_BASE);
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ulong lsize = CONFIG_SYS_DCACHE_LINE_SIZE;
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ulong addr;
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u32 val;
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/* Enable CCA override. Set to uncached */
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val = readl(cm_base + GCR_BASE);
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val &= ~CCA_DEFAULT_OVR_MASK;
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val |= CCA_DEFAULT_OVREN | (2 << CCA_DEFAULT_OVR_SHIFT);
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writel(val, cm_base + GCR_BASE);
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/* Initialize L1 I-Cache */
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write_c0_taglo(0);
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write_c0_taghi(0);
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for (addr = 0; addr < CONFIG_SYS_ICACHE_SIZE; addr += lsize)
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mips_cache(INDEX_STORE_TAG_I, (void *)addr);
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/* Initialize L1 D-Cache */
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write_c0_dtaglo(0);
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__write_32bit_c0_register($29, 2, 0); /* dtaghi */
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for (addr = 0; addr < CONFIG_SYS_DCACHE_SIZE; addr += lsize)
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mips_cache(INDEX_STORE_TAG_D, (void *)addr);
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/* Initialize L2 Cache */
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write_c0_staglo(0);
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__write_32bit_c0_register($29, 4, 0); /* staghi */
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for (addr = 0; addr < (256 << 10); addr += lsize)
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mips_cache(INDEX_STORE_TAG_SD, (void *)addr);
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/* Dsiable CCA override */
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val = readl(cm_base + GCR_BASE);
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val &= ~(CCA_DEFAULT_OVR_MASK | CCA_DEFAULT_OVREN);
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writel(val, cm_base + GCR_BASE);
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/* Set KSEG0 to non-coherent cached (important!) */
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val = read_c0_config();
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val &= ~CONF_CM_CMASK;
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val |= CONF_CM_CACHABLE_NONCOHERENT;
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write_c0_config(val);
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execution_hazard_barrier();
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/* Again, invalidate L1 D-Cache */
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for (addr = 0; addr < CONFIG_SYS_DCACHE_SIZE; addr += lsize)
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mips_cache(INDEX_WRITEBACK_INV_D, (void *)addr);
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/* Invalidate L1 I-Cache */
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for (addr = 0; addr < CONFIG_SYS_ICACHE_SIZE; addr += lsize)
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mips_cache(INDEX_INVALIDATE_I, (void *)addr);
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/* Disable L2 cache bypass */
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val = read_c0_config2();
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val &= ~MIPS_CONF_IMPL;
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write_c0_config2(val);
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execution_hazard_barrier();
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}
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void __noreturn tpl_main(void)
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{
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const struct legacy_img_hdr *hdr = (const struct legacy_img_hdr *)__image_copy_end;
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image_entry_noargs_t image_entry;
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u32 loadaddr, size;
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uintptr_t data;
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/* Initialize the cache first */
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mt7621_cache_init();
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if (image_get_magic(hdr) != IH_MAGIC)
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goto failed;
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loadaddr = image_get_load(hdr);
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size = image_get_size(hdr);
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image_entry = (image_entry_noargs_t)image_get_ep(hdr);
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/* Load TPL image to L2 cache */
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data = (uintptr_t)__image_copy_end + sizeof(struct legacy_img_hdr);
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fill_lock_l2cache(data, loadaddr, size);
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/* Jump to SPL */
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image_entry();
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failed:
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for (;;)
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;
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}
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