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https://github.com/AsahiLinux/u-boot
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6e38e2ea79
In all the ZynqMP boards dts files tx-buswidth is by default set to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4 in ZynqMP boards dts files. This would enable the spi-nor framework to issue 1-4-4 write commands instead of 1-1-1. This will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/ad61199f55e5e00f29de6206d9d1872a52a7657e.1652193179.git.michal.simek@amd.com
220 lines
3.1 KiB
Text
220 lines
3.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* dts file for Xilinx ZynqMP zc1751-xm018-dc4
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*
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* (C) Copyright 2015 - 2021, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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/ {
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model = "ZynqMP zc1751-xm018-dc4";
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compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem0;
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ethernet1 = &gem1;
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ethernet2 = &gem2;
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ethernet3 = &gem3;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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rtc0 = &rtc;
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serial0 = &uart0;
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serial1 = &uart1;
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spi0 = &qspi;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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};
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&can0 {
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status = "okay";
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};
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&can1 {
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status = "okay";
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};
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&fpd_dma_chan1 {
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status = "okay";
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};
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&fpd_dma_chan2 {
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status = "okay";
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};
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&fpd_dma_chan3 {
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status = "okay";
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};
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&fpd_dma_chan4 {
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status = "okay";
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};
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&fpd_dma_chan5 {
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status = "okay";
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};
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&fpd_dma_chan6 {
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status = "okay";
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};
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&fpd_dma_chan7 {
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status = "okay";
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};
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&fpd_dma_chan8 {
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status = "okay";
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};
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&lpd_dma_chan1 {
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status = "okay";
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};
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&lpd_dma_chan2 {
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status = "okay";
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};
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&lpd_dma_chan3 {
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status = "okay";
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};
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&lpd_dma_chan4 {
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status = "okay";
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};
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&lpd_dma_chan5 {
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status = "okay";
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};
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&lpd_dma_chan6 {
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status = "okay";
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};
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&lpd_dma_chan7 {
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status = "okay";
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};
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&lpd_dma_chan8 {
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status = "okay";
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};
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&gem0 {
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status = "okay";
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy0>;
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ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
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reg = <0>;
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};
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ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
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reg = <7>;
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};
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ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
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reg = <3>;
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};
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ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
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reg = <8>;
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};
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};
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&gem1 {
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status = "okay";
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy7>;
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};
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&gem2 {
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status = "okay";
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy3>;
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};
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&gem3 {
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status = "okay";
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy8>;
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};
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&gpio {
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status = "okay";
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};
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&gpu {
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status = "okay";
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};
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&i2c0 {
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clock-frequency = <400000>;
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <400000>;
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status = "okay";
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};
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&qspi {
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status = "okay";
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flash@0 {
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compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>; /* also DUAL configuration possible */
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spi-max-frequency = <108000000>; /* Based on DC1 spec */
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partition@0 { /* for testing purpose */
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label = "qspi-fsbl-uboot";
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reg = <0x0 0x100000>;
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};
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partition@100000 { /* for testing purpose */
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label = "qspi-linux";
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reg = <0x100000 0x500000>;
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};
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partition@600000 { /* for testing purpose */
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label = "qspi-device-tree";
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reg = <0x600000 0x20000>;
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};
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partition@620000 { /* for testing purpose */
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label = "qspi-rootfs";
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reg = <0x620000 0x5E0000>;
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};
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};
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};
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&rtc {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&watchdog0 {
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status = "okay";
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};
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&zynqmp_dpdma {
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status = "okay";
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};
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&zynqmp_dpsub {
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status = "okay";
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};
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