mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-29 10:52:09 +00:00
c7ea9612df
The assigned-clock no longer have to be dropped, the clock are now defined in clk-imx8mp.c and used by DWMAC driver to configure the DWMAC clock. Drop the workarounds from U-Boot specific DT extras. Signed-off-by: Marek Vasut <marex@denx.de>
135 lines
1.4 KiB
Text
135 lines
1.4 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2022 Marek Vasut <marex@denx.de>
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*/
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#include "imx8mp-u-boot.dtsi"
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/ {
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aliases {
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eeprom0 = &eeprom0;
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eeprom1 = &eeprom1;
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mmc0 = &usdhc2; /* MicroSD */
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mmc1 = &usdhc3; /* eMMC */
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mmc2 = &usdhc1; /* SDIO */
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};
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config {
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dh,ram-coding-gpios = <&gpio3 22 0>, <&gpio3 23 0>, <&gpio3 24 0>;
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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bootph-pre-ram;
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};
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};
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&buck4 {
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bootph-pre-ram;
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};
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&buck5 {
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bootph-pre-ram;
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};
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&gpio1 {
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bootph-pre-ram;
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};
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&gpio2 {
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bootph-pre-ram;
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};
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&gpio3 {
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bootph-pre-ram;
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};
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&gpio4 {
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bootph-pre-ram;
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};
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&gpio5 {
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bootph-pre-ram;
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};
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&i2c3 {
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bootph-pre-ram;
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};
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&pinctrl_i2c3 {
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bootph-pre-ram;
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};
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&pinctrl_i2c3_gpio {
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bootph-pre-ram;
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};
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&pinctrl_pmic {
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bootph-pre-ram;
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};
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&pinctrl_uart1 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2_100mhz {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2_200mhz {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2_vmmc {
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bootph-pre-ram;
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};
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&pinctrl_usdhc3 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc3_100mhz {
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bootph-pre-ram;
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};
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&pinctrl_usdhc3_100mhz {
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bootph-pre-ram;
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};
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&pmic {
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bootph-pre-ram;
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regulators {
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bootph-pre-ram;
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};
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};
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®_usdhc2_vmmc {
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bootph-pre-ram;
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};
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&uart1 {
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bootph-pre-ram;
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};
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/* SDIO WiFi */
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&usdhc1 {
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status = "disabled";
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};
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&usdhc2 {
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bootph-pre-ram;
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};
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&usdhc3 {
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bootph-pre-ram;
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};
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&wdog1 {
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bootph-pre-ram;
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};
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