mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-29 22:43:10 +00:00
bd8851c5b4
The 'base' GPIO controller property is unused in u-boot and Linux. It is also not documented in the binding. So drop it. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Masahisa Kojima <masahisa.kojima@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
594 lines
17 KiB
Text
594 lines
17 KiB
Text
/** @file
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* Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*/
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/* These are added for U-Boot to avoid compilation error */
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#define PcdNetsecEepromBase 0x08080000
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#define FixedPcdGet32(n) n
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#define GIC_SPI 0
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#define GIC_PPI 1
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#define IRQ_TYPE_NONE 0
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#define IRQ_TYPE_EDGE_RISING 1
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#define IRQ_TYPE_EDGE_FALLING 2
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#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
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#define IRQ_TYPE_LEVEL_HIGH 4
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#define IRQ_TYPE_LEVEL_LOW 8
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#define GPIO_ACTIVE_HIGH 0
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#define GPIO_ACTIVE_LOW 1
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &soc_uart0;
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serial1 = &fuart;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU4: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x200>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU5: cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x201>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU6: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x300>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU7: cpu@301 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x301>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU8: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x400>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU9: cpu@401 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x401>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU10: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x500>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU11: cpu@501 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x501>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU12: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x600>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU13: cpu@601 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x601>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU14: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x700>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU15: cpu@701 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x701>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU16: cpu@800 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x800>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU17: cpu@801 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x801>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU18: cpu@900 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x900>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU19: cpu@901 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x901>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU20: cpu@a00 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0xa00>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU21: cpu@a01 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0xa01>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU22: cpu@b00 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0xb00>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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CPU23: cpu@b01 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0xb01>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU2>;
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};
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core1 {
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cpu = <&CPU3>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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};
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cluster3 {
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core0 {
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cpu = <&CPU6>;
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};
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core1 {
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cpu = <&CPU7>;
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};
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};
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cluster4 {
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core0 {
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cpu = <&CPU8>;
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};
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core1 {
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cpu = <&CPU9>;
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};
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};
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cluster5 {
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core0 {
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cpu = <&CPU10>;
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};
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core1 {
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cpu = <&CPU11>;
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};
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};
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cluster6 {
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core0 {
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cpu = <&CPU12>;
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};
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core1 {
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cpu = <&CPU13>;
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};
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};
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cluster7 {
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core0 {
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cpu = <&CPU14>;
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};
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core1 {
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cpu = <&CPU15>;
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};
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};
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cluster8 {
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core0 {
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cpu = <&CPU16>;
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};
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core1 {
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cpu = <&CPU17>;
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};
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};
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cluster9 {
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core0 {
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cpu = <&CPU18>;
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};
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core1 {
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cpu = <&CPU19>;
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};
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};
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cluster10 {
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core0 {
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cpu = <&CPU20>;
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};
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core1 {
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cpu = <&CPU21>;
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};
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};
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cluster11 {
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core0 {
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cpu = <&CPU22>;
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};
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core1 {
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cpu = <&CPU23>;
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};
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};
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};
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};
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idle-states {
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entry-method = "psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <300>;
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exit-latency-us = <1200>;
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min-residency-us = <2000>;
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local-timer-stop;
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};
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x1010000>;
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entry-latency-us = <400>;
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exit-latency-us = <1200>;
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min-residency-us = <2500>;
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local-timer-stop;
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};
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};
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gic: interrupt-controller@30000000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x30000000 0x0 0x10000>, // GICD
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<0x0 0x30400000 0x0 0x300000>, // GICR
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<0x0 0x2c000000 0x0 0x2000>, // GICC
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<0x0 0x2c010000 0x0 0x1000>, // GICH
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<0x0 0x2c020000 0x0 0x10000>; // GICV
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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its: msi-controller@30020000 {
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compatible = "arm,gic-v3-its";
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reg = <0x0 0x30020000 0x0 0x20000>;
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#msi-cells = <1>;
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msi-controller;
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socionext,synquacer-pre-its = <0x58000000 0x200000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, // secure
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, // non-secure
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, // virtual
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; // HYP
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};
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timer@2a810000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x2a810000 0x0 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x2a810000 0x30000>;
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frame@20000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x20000 0x10000>;
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};
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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clk_uart: refclk62500khz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <62500000>;
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clock-output-names = "uartclk";
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};
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clk_apb: refclk100mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "apb_pclk";
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};
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soc_uart0: serial@2a400000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x2a400000 0x0 0x1000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_uart>, <&clk_apb>;
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clock-names = "uartclk", "apb_pclk";
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};
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fuart: serial@51040000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x51040000 0x0 0x1000>;
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_uart>, <&clk_apb>;
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clock-names = "baudclk", "apb_pclk";
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reg-io-width = <4>;
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reg-shift = <2>;
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};
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clk_netsec: refclk250mhz {
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compatible = "fixed-clock";
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clock-frequency = <250000000>;
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#clock-cells = <0>;
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};
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netsec: ethernet@522d0000 {
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compatible = "socionext,synquacer-netsec";
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reg = <0 0x522d0000 0x0 0x10000>,
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<0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_netsec>;
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clock-names = "phy_ref_clk";
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max-speed = <1000>;
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max-frame-size = <9000>;
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phy-handle = <&phy_netsec>;
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dma-coherent;
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mdio_netsec: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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smmu: iommu@582c0000 {
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compatible = "arm,mmu-500", "arm,smmu-v2";
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reg = <0x0 0x582c0000 0x0 0x10000>;
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#global-interrupts = <1>;
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interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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pcie0: pcie@60000000 {
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compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
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device_type = "pci";
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reg = <0x0 0x60000000 0x0 0x7f00000>;
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bus-range = <0x0 0x7e>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x1000000 0x00 0x00000000 0x00 0x67f00000 0x0 0x00010000>,
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<0x2000000 0x00 0x68000000 0x00 0x68000000 0x0 0x08000000>,
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<0x3000000 0x3e 0x00000000 0x3e 0x00000000 0x1 0x00000000>;
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#interrupt-cells = <0x1>;
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interrupt-map-mask = <0x0 0x0 0x0 0x0>;
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interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
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msi-map = <0x000 &its 0x0 0x7f00>;
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dma-coherent;
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status = "disabled";
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};
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pcie1: pcie@70000000 {
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compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
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device_type = "pci";
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reg = <0x0 0x70000000 0x0 0x7f00000>;
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bus-range = <0x0 0x7e>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x1000000 0x00 0x00000000 0x00 0x77f00000 0x0 0x00010000>,
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<0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>,
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<0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
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#interrupt-cells = <0x1>;
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interrupt-map-mask = <0x0 0x0 0x0 0x0>;
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interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
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msi-map = <0x0 &its 0x10000 0x7f00>;
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dma-coherent;
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status = "disabled";
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};
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gpio: gpio@51000000 {
|
|
compatible = "socionext,synquacer-gpio", "fujitsu,mb86s70-gpio";
|
|
reg = <0x0 0x51000000 0x0 0x100>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
clocks = <&clk_apb>;
|
|
};
|
|
|
|
exiu: interrupt-controller@510c0000 {
|
|
compatible = "socionext,synquacer-exiu";
|
|
reg = <0x0 0x510c0000 0x0 0x20>;
|
|
interrupt-controller;
|
|
interrupt-parent = <&gic>;
|
|
#interrupt-cells = <3>;
|
|
socionext,spi-base = <112>;
|
|
};
|
|
|
|
clk_alw_b_0: bclk200 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <200000000>;
|
|
clock-output-names = "sd_bclk";
|
|
};
|
|
|
|
clk_alw_c_0: sd4clk800 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <800000000>;
|
|
clock-output-names = "sd_sd4clk";
|
|
};
|
|
|
|
sdhci: mmc@52300000 {
|
|
compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0";
|
|
reg = <0 0x52300000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-width = <8>;
|
|
cap-mmc-highspeed;
|
|
fujitsu,cmd-dat-delay-select;
|
|
clocks = <&clk_alw_c_0 &clk_alw_b_0>;
|
|
clock-names = "core", "iface";
|
|
dma-coherent;
|
|
status = "disabled";
|
|
};
|
|
|
|
clk_alw_1_8: spi_ihclk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <125000000>;
|
|
clock-output-names = "iHCLK";
|
|
};
|
|
|
|
spi: spi@54810000 {
|
|
compatible = "socionext,synquacer-spi";
|
|
reg = <0x0 0x54810000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_alw_1_8>;
|
|
clock-names = "iHCLK";
|
|
socionext,use-rtm;
|
|
socionext,set-aces;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
clk_i2c: i2c_pclk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <62500000>;
|
|
clock-output-names = "pclk";
|
|
};
|
|
|
|
i2c: i2c@51210000 {
|
|
compatible = "socionext,synquacer-i2c";
|
|
reg = <0x0 0x51210000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_i2c>;
|
|
clock-names = "pclk";
|
|
clock-frequency = <400000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
tpm: tpm_tis@10000000 {
|
|
compatible = "socionext,synquacer-tpm-mmio";
|
|
reg = <0x0 0x10000000 0x0 0x5000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
firmware {
|
|
optee {
|
|
compatible = "linaro,optee-tz";
|
|
method = "smc";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "synquacer-sc2a11-caches.dtsi"
|