mirror of
https://github.com/AsahiLinux/u-boot
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285 lines
6.9 KiB
C
285 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
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* (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <common.h>
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#include <init.h>
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#include <log.h>
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#include <net.h>
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#include <asm/arch/boot.h>
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#include <asm/arch/eth.h>
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#include <asm/arch/g12a.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/meson-vpu.h>
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#include <asm/io.h>
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#include <asm/armv8/mmu.h>
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#include <linux/sizes.h>
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#include <usb.h>
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#include <linux/usb/otg.h>
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#include <asm/arch/usb.h>
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#include <usb/dwc2_udc.h>
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#include <phy.h>
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#include <clk.h>
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DECLARE_GLOBAL_DATA_PTR;
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int meson_get_boot_device(void)
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{
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return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE;
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}
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/* Configure the reserved memory zones exported by the secure registers
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* into EFI and DTB reserved memory entries.
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*/
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void meson_init_reserved_memory(void *fdt)
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{
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u64 bl31_size, bl31_start;
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u64 bl32_size, bl32_start;
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u32 reg;
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/*
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* Get ARM Trusted Firmware reserved memory zones in :
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* - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
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* - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
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* - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
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*/
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reg = readl(G12A_AO_SEC_GP_CFG3);
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bl31_size = ((reg & G12A_AO_BL31_RSVMEM_SIZE_MASK)
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>> G12A_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
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bl32_size = (reg & G12A_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
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bl31_start = readl(G12A_AO_SEC_GP_CFG5);
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bl32_start = readl(G12A_AO_SEC_GP_CFG4);
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/* Add BL31 reserved zone */
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if (bl31_start && bl31_size)
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meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
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/* Add BL32 reserved zone */
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if (bl32_start && bl32_size)
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meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
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#if defined(CONFIG_VIDEO_MESON)
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meson_vpu_rsv_fb(fdt);
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#endif
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}
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phys_size_t get_effective_memsize(void)
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{
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/* Size is reported in MiB, convert it in bytes */
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return min(((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
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>> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M, 0xf5000000);
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}
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static struct mm_region g12a_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0xf5000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xf5000000UL,
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.phys = 0xf5000000UL,
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.size = 0x0b000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = g12a_mem_map;
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static void g12a_enable_external_mdio(void)
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{
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writel(0x0, ETH_PHY_CNTL2);
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}
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static void g12a_enable_internal_mdio(void)
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{
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/* Fire up the PHY PLL */
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writel(0x29c0040a, ETH_PLL_CNTL0);
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writel(0x927e0000, ETH_PLL_CNTL1);
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writel(0xac5f49e5, ETH_PLL_CNTL2);
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writel(0x00000000, ETH_PLL_CNTL3);
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writel(0x00000000, ETH_PLL_CNTL4);
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writel(0x20200000, ETH_PLL_CNTL5);
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writel(0x0000c002, ETH_PLL_CNTL6);
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writel(0x00000023, ETH_PLL_CNTL7);
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writel(0x39c0040a, ETH_PLL_CNTL0);
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writel(0x19c0040a, ETH_PLL_CNTL0);
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/* Select the internal MDIO */
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writel(0x33000180, ETH_PHY_CNTL0);
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writel(0x00074043, ETH_PHY_CNTL1);
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writel(0x00000260, ETH_PHY_CNTL2);
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}
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/* Configure the Ethernet MAC with the requested interface mode
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* with some optional flags.
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*/
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void meson_eth_init(phy_interface_t mode, unsigned int flags)
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{
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switch (mode) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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/* Set RGMII mode */
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setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII |
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G12A_ETH_REG_0_TX_PHASE(1) |
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G12A_ETH_REG_0_TX_RATIO(4) |
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G12A_ETH_REG_0_PHY_CLK_EN |
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G12A_ETH_REG_0_CLK_EN);
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g12a_enable_external_mdio();
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break;
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case PHY_INTERFACE_MODE_RMII:
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/* Set RMII mode */
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out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII |
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G12A_ETH_REG_0_INVERT_RMII_CLK |
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G12A_ETH_REG_0_CLK_EN);
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/* Use G12A RMII Internal PHY */
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if (flags & MESON_USE_INTERNAL_RMII_PHY)
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g12a_enable_internal_mdio();
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else
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g12a_enable_external_mdio();
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break;
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default:
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printf("Invalid Ethernet interface mode\n");
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return;
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}
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/* Enable power gate */
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clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK);
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}
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#if CONFIG_IS_ENABLED(USB_DWC3_MESON_G12A) && \
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CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
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static struct dwc2_plat_otg_data meson_g12a_dwc2_data;
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int board_usb_init(int index, enum usb_init_type init)
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{
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struct fdtdec_phandle_args args;
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const void *blob = gd->fdt_blob;
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int node, dwc2_node;
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struct udevice *dev, *clk_dev;
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struct clk clk;
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int ret;
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/* find the usb glue node */
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node = fdt_node_offset_by_compatible(blob, -1,
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"amlogic,meson-g12a-usb-ctrl");
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if (node < 0) {
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debug("Not found usb-control node\n");
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return -ENODEV;
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}
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if (!fdtdec_get_is_enabled(blob, node)) {
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debug("usb is disabled in the device tree\n");
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return -ENODEV;
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}
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ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
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if (ret) {
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debug("Not found usb-control device\n");
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return ret;
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}
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/* find the dwc2 node */
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dwc2_node = fdt_node_offset_by_compatible(blob, node,
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"amlogic,meson-g12a-usb");
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if (dwc2_node < 0) {
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debug("Not found dwc2 node\n");
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return -ENODEV;
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}
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if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
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debug("dwc2 is disabled in the device tree\n");
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return -ENODEV;
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}
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meson_g12a_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
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if (meson_g12a_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
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debug("usbotg: can't get base address\n");
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return -ENODATA;
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}
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/* Enable clock */
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ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
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"#clock-cells", 0, 0, &args);
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if (ret) {
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debug("usbotg has no clocks defined in the device tree\n");
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return ret;
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}
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ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
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if (ret)
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return ret;
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if (args.args_count != 1) {
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debug("Can't find clock ID in the device tree\n");
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return -ENODATA;
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}
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clk.dev = clk_dev;
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clk.id = args.args[0];
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ret = clk_enable(&clk);
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if (ret) {
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debug("Failed to enable usbotg clock\n");
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return ret;
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}
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meson_g12a_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
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"g-rx-fifo-size", 0);
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meson_g12a_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
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"g-np-tx-fifo-size", 0);
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meson_g12a_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
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"g-tx-fifo-size", 0);
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/* Switch to peripheral mode */
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ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_PERIPHERAL);
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if (ret)
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return ret;
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return dwc2_udc_probe(&meson_g12a_dwc2_data);
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}
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int board_usb_cleanup(int index, enum usb_init_type init)
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{
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const void *blob = gd->fdt_blob;
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struct udevice *dev;
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int node;
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int ret;
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/* find the usb glue node */
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node = fdt_node_offset_by_compatible(blob, -1,
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"amlogic,meson-g12a-usb-ctrl");
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if (node < 0)
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return -ENODEV;
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if (!fdtdec_get_is_enabled(blob, node))
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return -ENODEV;
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ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
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if (ret)
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return ret;
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/* Switch to OTG mode */
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ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_HOST);
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if (ret)
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return ret;
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return 0;
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}
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#endif
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