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https://github.com/AsahiLinux/u-boot
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983c1db04c
Adapt the existing AT91CAP9 code to the new headers and APIs. Signed-off-by: Stelian Pop <stelian@popies.net>
160 lines
4.9 KiB
C
160 lines
4.9 KiB
C
/*
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* Driver for ATMEL DataFlash support
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* Author : Hamid Ikdoumi (Atmel)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/at91_spi.h>
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#ifdef CONFIG_HAS_DATAFLASH
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#include <dataflash.h>
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#define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
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#define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 0: NPCS0%1101 */
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#define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
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void AT91F_SpiInit(void)
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{
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/* Reset the SPI */
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writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR);
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/* Configure SPI in Master Mode with No CS selected !!! */
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writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS,
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AT91_BASE_SPI + AT91_SPI_MR);
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/* Configure CS0 */
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writel(AT91_SPI_NCPHA |
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(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
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(AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
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((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
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AT91_BASE_SPI + AT91_SPI_CSR(0));
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#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS1
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/* Configure CS1 */
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writel(AT91_SPI_NCPHA |
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(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
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(AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
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((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
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AT91_BASE_SPI + AT91_SPI_CSR(1));
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#endif
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#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS3
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/* Configure CS3 */
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writel(AT91_SPI_NCPHA |
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(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
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(AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
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((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
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AT91_BASE_SPI + AT91_SPI_CSR(3));
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#endif
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/* SPI_Enable */
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writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
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while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_SPIENS));
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/*
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* Add tempo to get SPI in a safe state.
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* Should not be needed for new silicon (Rev B)
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*/
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udelay(500000);
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readl(AT91_BASE_SPI + AT91_SPI_SR);
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readl(AT91_BASE_SPI + AT91_SPI_RDR);
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}
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void AT91F_SpiEnable(int cs)
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{
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unsigned long mode;
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switch (cs) {
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case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
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mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
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mode &= 0xFFF0FFFF;
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writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
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AT91_BASE_SPI + AT91_SPI_MR);
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break;
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case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */
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mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
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mode &= 0xFFF0FFFF;
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writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
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AT91_BASE_SPI + AT91_SPI_MR);
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break;
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case 3:
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mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
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mode &= 0xFFF0FFFF;
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writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
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AT91_BASE_SPI + AT91_SPI_MR);
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break;
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}
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/* SPI_Enable */
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writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
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}
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unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
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unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
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{
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unsigned int timeout;
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pDesc->state = BUSY;
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writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
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/* Initialize the Transmit and Receive Pointer */
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writel((unsigned int)pDesc->rx_cmd_pt, AT91_BASE_SPI + AT91_SPI_RPR);
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writel((unsigned int)pDesc->tx_cmd_pt, AT91_BASE_SPI + AT91_SPI_TPR);
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/* Intialize the Transmit and Receive Counters */
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writel(pDesc->rx_cmd_size, AT91_BASE_SPI + AT91_SPI_RCR);
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writel(pDesc->tx_cmd_size, AT91_BASE_SPI + AT91_SPI_TCR);
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if (pDesc->tx_data_size != 0) {
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/* Initialize the Next Transmit and Next Receive Pointer */
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writel((unsigned int)pDesc->rx_data_pt, AT91_BASE_SPI + AT91_SPI_RNPR);
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writel((unsigned int)pDesc->tx_data_pt, AT91_BASE_SPI + AT91_SPI_TNPR);
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/* Intialize the Next Transmit and Next Receive Counters */
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writel(pDesc->rx_data_size, AT91_BASE_SPI + AT91_SPI_RNCR);
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writel(pDesc->tx_data_size, AT91_BASE_SPI + AT91_SPI_TNCR);
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}
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/* arm simple, non interrupt dependent timer */
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reset_timer_masked();
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timeout = 0;
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writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR);
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while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
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((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT));
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writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
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pDesc->state = IDLE;
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if (timeout >= CFG_SPI_WRITE_TOUT) {
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printf("Error Timeout\n\r");
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return DATAFLASH_ERROR;
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}
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return DATAFLASH_OK;
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}
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#endif
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