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https://github.com/AsahiLinux/u-boot
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98036b0d70
This patch includes misc changes to already present Octeon MIPS header files, which are necessary for the upcoming ethernet support. The changes are mostly: - DM GPIO & I2C infrastructure - Coding style cleanup while reworking the headers Signed-off-by: Stefan Roese <sr@denx.de>
529 lines
14 KiB
C
529 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*
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* Interface to the CN78XX Free Pool Allocator, a.k.a. FPA3
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*/
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#include "cvmx-address.h"
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#include "cvmx-fpa-defs.h"
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#include "cvmx-scratch.h"
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#ifndef __CVMX_FPA3_H__
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#define __CVMX_FPA3_H__
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typedef struct {
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unsigned res0 : 6;
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unsigned node : 2;
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unsigned res1 : 2;
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unsigned lpool : 6;
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unsigned valid_magic : 16;
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} cvmx_fpa3_pool_t;
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typedef struct {
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unsigned res0 : 6;
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unsigned node : 2;
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unsigned res1 : 6;
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unsigned laura : 10;
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unsigned valid_magic : 16;
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} cvmx_fpa3_gaura_t;
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#define CVMX_FPA3_VALID_MAGIC 0xf9a3
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#define CVMX_FPA3_INVALID_GAURA ((cvmx_fpa3_gaura_t){ 0, 0, 0, 0, 0 })
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#define CVMX_FPA3_INVALID_POOL ((cvmx_fpa3_pool_t){ 0, 0, 0, 0, 0 })
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static inline bool __cvmx_fpa3_aura_valid(cvmx_fpa3_gaura_t aura)
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{
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if (aura.valid_magic != CVMX_FPA3_VALID_MAGIC)
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return false;
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return true;
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}
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static inline bool __cvmx_fpa3_pool_valid(cvmx_fpa3_pool_t pool)
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{
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if (pool.valid_magic != CVMX_FPA3_VALID_MAGIC)
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return false;
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return true;
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}
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static inline cvmx_fpa3_gaura_t __cvmx_fpa3_gaura(int node, int laura)
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{
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cvmx_fpa3_gaura_t aura;
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if (node < 0)
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node = cvmx_get_node_num();
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if (laura < 0)
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return CVMX_FPA3_INVALID_GAURA;
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aura.node = node;
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aura.laura = laura;
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aura.valid_magic = CVMX_FPA3_VALID_MAGIC;
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return aura;
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}
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static inline cvmx_fpa3_pool_t __cvmx_fpa3_pool(int node, int lpool)
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{
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cvmx_fpa3_pool_t pool;
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if (node < 0)
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node = cvmx_get_node_num();
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if (lpool < 0)
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return CVMX_FPA3_INVALID_POOL;
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pool.node = node;
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pool.lpool = lpool;
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pool.valid_magic = CVMX_FPA3_VALID_MAGIC;
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return pool;
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}
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#undef CVMX_FPA3_VALID_MAGIC
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/**
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* Structure describing the data format used for stores to the FPA.
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*/
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typedef union {
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u64 u64;
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struct {
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u64 scraddr : 8;
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u64 len : 8;
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u64 did : 8;
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u64 addr : 40;
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} s;
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struct {
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u64 scraddr : 8;
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u64 len : 8;
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u64 did : 8;
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u64 node : 4;
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u64 red : 1;
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u64 reserved2 : 9;
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u64 aura : 10;
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u64 reserved3 : 16;
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} cn78xx;
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} cvmx_fpa3_iobdma_data_t;
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/**
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* Struct describing load allocate operation addresses for FPA pool.
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*/
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union cvmx_fpa3_load_data {
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u64 u64;
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struct {
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u64 seg : 2;
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u64 reserved1 : 13;
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u64 io : 1;
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u64 did : 8;
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u64 node : 4;
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u64 red : 1;
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u64 reserved2 : 9;
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u64 aura : 10;
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u64 reserved3 : 16;
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};
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};
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typedef union cvmx_fpa3_load_data cvmx_fpa3_load_data_t;
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/**
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* Struct describing store free operation addresses from FPA pool.
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*/
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union cvmx_fpa3_store_addr {
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u64 u64;
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struct {
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u64 seg : 2;
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u64 reserved1 : 13;
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u64 io : 1;
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u64 did : 8;
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u64 node : 4;
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u64 reserved2 : 10;
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u64 aura : 10;
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u64 fabs : 1;
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u64 reserved3 : 3;
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u64 dwb_count : 9;
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u64 reserved4 : 3;
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};
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};
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typedef union cvmx_fpa3_store_addr cvmx_fpa3_store_addr_t;
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enum cvmx_fpa3_pool_alignment_e {
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FPA_NATURAL_ALIGNMENT,
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FPA_OFFSET_ALIGNMENT,
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FPA_OPAQUE_ALIGNMENT
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};
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#define CVMX_FPA3_AURAX_LIMIT_MAX ((1ull << 40) - 1)
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/**
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* @INTERNAL
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* Accessor functions to return number of POOLS in an FPA3
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* depending on SoC model.
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* The number is per-node for models supporting multi-node configurations.
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*/
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static inline int cvmx_fpa3_num_pools(void)
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{
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if (OCTEON_IS_MODEL(OCTEON_CN78XX))
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return 64;
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if (OCTEON_IS_MODEL(OCTEON_CNF75XX))
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return 32;
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if (OCTEON_IS_MODEL(OCTEON_CN73XX))
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return 32;
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printf("ERROR: %s: Unknowm model\n", __func__);
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return -1;
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}
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/**
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* @INTERNAL
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* Accessor functions to return number of AURAS in an FPA3
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* depending on SoC model.
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* The number is per-node for models supporting multi-node configurations.
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*/
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static inline int cvmx_fpa3_num_auras(void)
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{
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if (OCTEON_IS_MODEL(OCTEON_CN78XX))
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return 1024;
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if (OCTEON_IS_MODEL(OCTEON_CNF75XX))
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return 512;
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if (OCTEON_IS_MODEL(OCTEON_CN73XX))
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return 512;
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printf("ERROR: %s: Unknowm model\n", __func__);
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return -1;
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}
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/**
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* Get the FPA3 POOL underneath FPA3 AURA, containing all its buffers
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*
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*/
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static inline cvmx_fpa3_pool_t cvmx_fpa3_aura_to_pool(cvmx_fpa3_gaura_t aura)
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{
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cvmx_fpa3_pool_t pool;
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cvmx_fpa_aurax_pool_t aurax_pool;
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aurax_pool.u64 = cvmx_read_csr_node(aura.node, CVMX_FPA_AURAX_POOL(aura.laura));
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pool = __cvmx_fpa3_pool(aura.node, aurax_pool.s.pool);
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return pool;
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}
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/**
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* Get a new block from the FPA pool
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*
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* @param aura - aura number
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* Return: pointer to the block or NULL on failure
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*/
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static inline void *cvmx_fpa3_alloc(cvmx_fpa3_gaura_t aura)
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{
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u64 address;
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cvmx_fpa3_load_data_t load_addr;
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load_addr.u64 = 0;
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load_addr.seg = CVMX_MIPS_SPACE_XKPHYS;
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load_addr.io = 1;
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load_addr.did = 0x29; /* Device ID. Indicates FPA. */
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load_addr.node = aura.node;
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load_addr.red = 0; /* Perform RED on allocation.
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* FIXME to use config option
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*/
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load_addr.aura = aura.laura;
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address = cvmx_read64_uint64(load_addr.u64);
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if (!address)
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return NULL;
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return cvmx_phys_to_ptr(address);
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}
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/**
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* Asynchronously get a new block from the FPA
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*
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* The result of cvmx_fpa_async_alloc() may be retrieved using
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* cvmx_fpa_async_alloc_finish().
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*
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* @param scr_addr Local scratch address to put response in. This is a byte
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* address but must be 8 byte aligned.
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* @param aura Global aura to get the block from
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*/
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static inline void cvmx_fpa3_async_alloc(u64 scr_addr, cvmx_fpa3_gaura_t aura)
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{
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cvmx_fpa3_iobdma_data_t data;
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/* Hardware only uses 64 bit aligned locations, so convert from byte
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* address to 64-bit index
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*/
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data.u64 = 0ull;
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data.cn78xx.scraddr = scr_addr >> 3;
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data.cn78xx.len = 1;
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data.cn78xx.did = 0x29;
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data.cn78xx.node = aura.node;
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data.cn78xx.aura = aura.laura;
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cvmx_scratch_write64(scr_addr, 0ull);
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CVMX_SYNCW;
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cvmx_send_single(data.u64);
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}
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/**
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* Retrieve the result of cvmx_fpa3_async_alloc
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*
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* @param scr_addr The Local scratch address. Must be the same value
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* passed to cvmx_fpa_async_alloc().
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*
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* @param aura Global aura the block came from. Must be the same value
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* passed to cvmx_fpa_async_alloc.
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*
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* Return: Pointer to the block or NULL on failure
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*/
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static inline void *cvmx_fpa3_async_alloc_finish(u64 scr_addr, cvmx_fpa3_gaura_t aura)
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{
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u64 address;
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CVMX_SYNCIOBDMA;
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address = cvmx_scratch_read64(scr_addr);
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if (cvmx_likely(address))
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return cvmx_phys_to_ptr(address);
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else
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/* Try regular alloc if async failed */
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return cvmx_fpa3_alloc(aura);
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}
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/**
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* Free a pointer back to the pool.
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*
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* @param aura global aura number
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* @param ptr physical address of block to free.
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* @param num_cache_lines Cache lines to invalidate
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*/
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static inline void cvmx_fpa3_free(void *ptr, cvmx_fpa3_gaura_t aura, unsigned int num_cache_lines)
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{
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cvmx_fpa3_store_addr_t newptr;
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cvmx_addr_t newdata;
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newdata.u64 = cvmx_ptr_to_phys(ptr);
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/* Make sure that any previous writes to memory go out before we free
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this buffer. This also serves as a barrier to prevent GCC from
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reordering operations to after the free. */
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CVMX_SYNCWS;
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newptr.u64 = 0;
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newptr.seg = CVMX_MIPS_SPACE_XKPHYS;
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newptr.io = 1;
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newptr.did = 0x29; /* Device id, indicates FPA */
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newptr.node = aura.node;
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newptr.aura = aura.laura;
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newptr.fabs = 0; /* Free absolute. FIXME to use config option */
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newptr.dwb_count = num_cache_lines;
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cvmx_write_io(newptr.u64, newdata.u64);
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}
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/**
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* Free a pointer back to the pool without flushing the write buffer.
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*
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* @param aura global aura number
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* @param ptr physical address of block to free.
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* @param num_cache_lines Cache lines to invalidate
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*/
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static inline void cvmx_fpa3_free_nosync(void *ptr, cvmx_fpa3_gaura_t aura,
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unsigned int num_cache_lines)
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{
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cvmx_fpa3_store_addr_t newptr;
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cvmx_addr_t newdata;
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newdata.u64 = cvmx_ptr_to_phys(ptr);
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/* Prevent GCC from reordering writes to (*ptr) */
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asm volatile("" : : : "memory");
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newptr.u64 = 0;
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newptr.seg = CVMX_MIPS_SPACE_XKPHYS;
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newptr.io = 1;
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newptr.did = 0x29; /* Device id, indicates FPA */
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newptr.node = aura.node;
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newptr.aura = aura.laura;
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newptr.fabs = 0; /* Free absolute. FIXME to use config option */
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newptr.dwb_count = num_cache_lines;
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cvmx_write_io(newptr.u64, newdata.u64);
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}
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static inline int cvmx_fpa3_pool_is_enabled(cvmx_fpa3_pool_t pool)
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{
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cvmx_fpa_poolx_cfg_t pool_cfg;
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if (!__cvmx_fpa3_pool_valid(pool))
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return -1;
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pool_cfg.u64 = cvmx_read_csr_node(pool.node, CVMX_FPA_POOLX_CFG(pool.lpool));
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return pool_cfg.cn78xx.ena;
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}
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static inline int cvmx_fpa3_config_red_params(unsigned int node, int qos_avg_en, int red_lvl_dly,
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int avg_dly)
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{
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cvmx_fpa_gen_cfg_t fpa_cfg;
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cvmx_fpa_red_delay_t red_delay;
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fpa_cfg.u64 = cvmx_read_csr_node(node, CVMX_FPA_GEN_CFG);
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fpa_cfg.s.avg_en = qos_avg_en;
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fpa_cfg.s.lvl_dly = red_lvl_dly;
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cvmx_write_csr_node(node, CVMX_FPA_GEN_CFG, fpa_cfg.u64);
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red_delay.u64 = cvmx_read_csr_node(node, CVMX_FPA_RED_DELAY);
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red_delay.s.avg_dly = avg_dly;
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cvmx_write_csr_node(node, CVMX_FPA_RED_DELAY, red_delay.u64);
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return 0;
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}
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/**
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* Gets the buffer size of the specified pool,
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*
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* @param aura Global aura number
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* Return: Returns size of the buffers in the specified pool.
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*/
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static inline int cvmx_fpa3_get_aura_buf_size(cvmx_fpa3_gaura_t aura)
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{
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cvmx_fpa3_pool_t pool;
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cvmx_fpa_poolx_cfg_t pool_cfg;
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int block_size;
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pool = cvmx_fpa3_aura_to_pool(aura);
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pool_cfg.u64 = cvmx_read_csr_node(pool.node, CVMX_FPA_POOLX_CFG(pool.lpool));
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block_size = pool_cfg.cn78xx.buf_size << 7;
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return block_size;
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}
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/**
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* Return the number of available buffers in an AURA
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*
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* @param aura to receive count for
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* Return: available buffer count
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*/
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static inline long long cvmx_fpa3_get_available(cvmx_fpa3_gaura_t aura)
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{
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cvmx_fpa3_pool_t pool;
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cvmx_fpa_poolx_available_t avail_reg;
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cvmx_fpa_aurax_cnt_t cnt_reg;
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cvmx_fpa_aurax_cnt_limit_t limit_reg;
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long long ret;
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pool = cvmx_fpa3_aura_to_pool(aura);
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/* Get POOL available buffer count */
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avail_reg.u64 = cvmx_read_csr_node(pool.node, CVMX_FPA_POOLX_AVAILABLE(pool.lpool));
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/* Get AURA current available count */
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cnt_reg.u64 = cvmx_read_csr_node(aura.node, CVMX_FPA_AURAX_CNT(aura.laura));
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limit_reg.u64 = cvmx_read_csr_node(aura.node, CVMX_FPA_AURAX_CNT_LIMIT(aura.laura));
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if (limit_reg.cn78xx.limit < cnt_reg.cn78xx.cnt)
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return 0;
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/* Calculate AURA-based buffer allowance */
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ret = limit_reg.cn78xx.limit - cnt_reg.cn78xx.cnt;
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/* Use POOL real buffer availability when less then allowance */
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if (ret > (long long)avail_reg.cn78xx.count)
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ret = avail_reg.cn78xx.count;
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return ret;
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}
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/**
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* Configure the QoS parameters of an FPA3 AURA
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*
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* @param aura is the FPA3 AURA handle
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* @param ena_bp enables backpressure when outstanding count exceeds 'bp_thresh'
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* @param ena_red enables random early discard when outstanding count exceeds 'pass_thresh'
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* @param pass_thresh is the maximum count to invoke flow control
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* @param drop_thresh is the count threshold to begin dropping packets
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* @param bp_thresh is the back-pressure threshold
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*
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*/
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static inline void cvmx_fpa3_setup_aura_qos(cvmx_fpa3_gaura_t aura, bool ena_red, u64 pass_thresh,
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u64 drop_thresh, bool ena_bp, u64 bp_thresh)
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{
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unsigned int shift = 0;
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u64 shift_thresh;
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cvmx_fpa_aurax_cnt_limit_t limit_reg;
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cvmx_fpa_aurax_cnt_levels_t aura_level;
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if (!__cvmx_fpa3_aura_valid(aura))
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return;
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/* Get AURAX count limit for validation */
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limit_reg.u64 = cvmx_read_csr_node(aura.node, CVMX_FPA_AURAX_CNT_LIMIT(aura.laura));
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if (pass_thresh < 256)
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pass_thresh = 255;
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if (drop_thresh <= pass_thresh || drop_thresh > limit_reg.cn78xx.limit)
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drop_thresh = limit_reg.cn78xx.limit;
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if (bp_thresh < 256 || bp_thresh > limit_reg.cn78xx.limit)
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bp_thresh = limit_reg.cn78xx.limit >> 1;
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shift_thresh = (bp_thresh > drop_thresh) ? bp_thresh : drop_thresh;
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/* Calculate shift so that the largest threshold fits in 8 bits */
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for (shift = 0; shift < (1 << 6); shift++) {
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if (0 == ((shift_thresh >> shift) & ~0xffull))
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break;
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};
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aura_level.u64 = cvmx_read_csr_node(aura.node, CVMX_FPA_AURAX_CNT_LEVELS(aura.laura));
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aura_level.s.pass = pass_thresh >> shift;
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aura_level.s.drop = drop_thresh >> shift;
|
|
aura_level.s.bp = bp_thresh >> shift;
|
|
aura_level.s.shift = shift;
|
|
aura_level.s.red_ena = ena_red;
|
|
aura_level.s.bp_ena = ena_bp;
|
|
cvmx_write_csr_node(aura.node, CVMX_FPA_AURAX_CNT_LEVELS(aura.laura), aura_level.u64);
|
|
}
|
|
|
|
cvmx_fpa3_gaura_t cvmx_fpa3_reserve_aura(int node, int desired_aura_num);
|
|
int cvmx_fpa3_release_aura(cvmx_fpa3_gaura_t aura);
|
|
cvmx_fpa3_pool_t cvmx_fpa3_reserve_pool(int node, int desired_pool_num);
|
|
int cvmx_fpa3_release_pool(cvmx_fpa3_pool_t pool);
|
|
int cvmx_fpa3_is_aura_available(int node, int aura_num);
|
|
int cvmx_fpa3_is_pool_available(int node, int pool_num);
|
|
|
|
cvmx_fpa3_pool_t cvmx_fpa3_setup_fill_pool(int node, int desired_pool, const char *name,
|
|
unsigned int block_size, unsigned int num_blocks,
|
|
void *buffer);
|
|
|
|
/**
|
|
* Function to attach an aura to an existing pool
|
|
*
|
|
* @param node - configure fpa on this node
|
|
* @param pool - configured pool to attach aura to
|
|
* @param desired_aura - pointer to aura to use, set to -1 to allocate
|
|
* @param name - name to register
|
|
* @param block_size - size of buffers to use
|
|
* @param num_blocks - number of blocks to allocate
|
|
*
|
|
* Return: configured gaura on success, CVMX_FPA3_INVALID_GAURA on failure
|
|
*/
|
|
cvmx_fpa3_gaura_t cvmx_fpa3_set_aura_for_pool(cvmx_fpa3_pool_t pool, int desired_aura,
|
|
const char *name, unsigned int block_size,
|
|
unsigned int num_blocks);
|
|
|
|
/**
|
|
* Function to setup and initialize a pool.
|
|
*
|
|
* @param node - configure fpa on this node
|
|
* @param desired_aura - aura to use, -1 for dynamic allocation
|
|
* @param name - name to register
|
|
* @param block_size - size of buffers in pool
|
|
* @param num_blocks - max number of buffers allowed
|
|
*/
|
|
cvmx_fpa3_gaura_t cvmx_fpa3_setup_aura_and_pool(int node, int desired_aura, const char *name,
|
|
void *buffer, unsigned int block_size,
|
|
unsigned int num_blocks);
|
|
|
|
int cvmx_fpa3_shutdown_aura_and_pool(cvmx_fpa3_gaura_t aura);
|
|
int cvmx_fpa3_shutdown_aura(cvmx_fpa3_gaura_t aura);
|
|
int cvmx_fpa3_shutdown_pool(cvmx_fpa3_pool_t pool);
|
|
const char *cvmx_fpa3_get_pool_name(cvmx_fpa3_pool_t pool);
|
|
int cvmx_fpa3_get_pool_buf_size(cvmx_fpa3_pool_t pool);
|
|
const char *cvmx_fpa3_get_aura_name(cvmx_fpa3_gaura_t aura);
|
|
|
|
#endif /* __CVMX_FPA3_H__ */
|