mirror of
https://github.com/AsahiLinux/u-boot
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65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
806 lines
20 KiB
C
806 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2012
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* Ивайло Димитров <freemangordon@abv.bg>
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*
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* (C) Copyright 2011-2012
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* Pali Rohár <pali@kernel.org>
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*
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* (C) Copyright 2010
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* Alistair Buxton <a.j.buxton@gmail.com>
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*
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* Derived from Beagle Board and 3430 SDP code:
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* (C) Copyright 2004-2008
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Sunil Kumar <sunilsaini05@gmail.com>
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* Shashi Ranjan <shashiranjanmca05@gmail.com>
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*
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <env.h>
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#include <init.h>
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#include <watchdog.h>
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#include <wdt.h>
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#include <malloc.h>
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#include <twl4030.h>
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#include <i2c.h>
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#include <video.h>
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#include <keyboard.h>
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#include <ns16550.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/setup.h>
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#include <asm/bitops.h>
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#include <asm/mach-types.h>
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#include <asm/omap_i2c.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mmc_host_def.h>
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#include "tag_omap.h"
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/* Needed for ROM SMC call */
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struct emu_hal_params_rx51 {
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u32 num_params;
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u32 param1;
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u32 param2;
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u32 param3;
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u32 param4;
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};
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#define ONENAND_GPMC_CONFIG1_RX51 0xfb001202
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#define ONENAND_GPMC_CONFIG2_RX51 0x00111100
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#define ONENAND_GPMC_CONFIG3_RX51 0x00020200
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#define ONENAND_GPMC_CONFIG4_RX51 0x11001102
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#define ONENAND_GPMC_CONFIG5_RX51 0x03101616
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#define ONENAND_GPMC_CONFIG6_RX51 0x90060000
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DECLARE_GLOBAL_DATA_PTR;
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const omap3_sysinfo sysinfo = {
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DDR_STACKED,
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"Nokia RX-51",
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"OneNAND"
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};
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/* This structure contains default omap tags needed for booting Maemo 5 */
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static struct tag_omap omap[] = {
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OMAP_TAG_UART_CONFIG(0x04),
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OMAP_TAG_SERIAL_CONSOLE_CONFIG(0x03, 0x01C200),
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OMAP_TAG_LCD_CONFIG("acx565akm", "internal", 90, 0x18),
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OMAP_TAG_GPIO_SWITCH_CONFIG("cam_focus", 0x44, 0x1, 0x2, 0x0),
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OMAP_TAG_GPIO_SWITCH_CONFIG("cam_launch", 0x45, 0x1, 0x2, 0x0),
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OMAP_TAG_GPIO_SWITCH_CONFIG("cam_shutter", 0x6e, 0x1, 0x0, 0x0),
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OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_apeslpx", 0x46, 0x2, 0x2, 0x0),
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OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_bsi", 0x9d, 0x2, 0x2, 0x0),
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OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_en", 0x4a, 0x2, 0x2, 0x0),
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OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_rst", 0x4b, 0x6, 0x2, 0x0),
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OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_rst_rq", 0x49, 0x6, 0x2, 0x0),
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OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_wddis", 0x0d, 0x2, 0x2, 0x0),
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OMAP_TAG_GPIO_SWITCH_CONFIG("headphone", 0xb1, 0x1, 0x1, 0x0),
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OMAP_TAG_GPIO_SWITCH_CONFIG("kb_lock", 0x71, 0x1, 0x0, 0x0),
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OMAP_TAG_GPIO_SWITCH_CONFIG("proximity", 0x59, 0x0, 0x0, 0x0),
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OMAP_TAG_GPIO_SWITCH_CONFIG("sleep_ind", 0xa2, 0x2, 0x2, 0x0),
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OMAP_TAG_GPIO_SWITCH_CONFIG("slide", GPIO_SLIDE, 0x0, 0x0, 0x0),
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OMAP_TAG_WLAN_CX3110X_CONFIG(0x25, 0xff, 87, 42, -1),
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OMAP_TAG_PARTITION_CONFIG("bootloader", 128 * 1024, 0x00000000, 0x00000003),
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OMAP_TAG_PARTITION_CONFIG("config", 384 * 1024, 0x00020000, 0x00000000),
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OMAP_TAG_PARTITION_CONFIG("log", 256 * 1024, 0x00080000, 0x00000000),
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OMAP_TAG_PARTITION_CONFIG("kernel", 2 * 1024*1024, 0x000c0000, 0x00000000),
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OMAP_TAG_PARTITION_CONFIG("initfs", 2 * 1024*1024, 0x002c0000, 0x00000000),
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OMAP_TAG_PARTITION_CONFIG("rootfs", 257280 * 1024, 0x004c0000, 0x00000000),
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OMAP_TAG_BOOT_REASON_CONFIG("pwr_key"),
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OMAP_TAG_VERSION_STR_CONFIG("product", "RX-51"),
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OMAP_TAG_VERSION_STR_CONFIG("hw-build", "2101"),
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OMAP_TAG_VERSION_STR_CONFIG("nolo", "1.4.14"),
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OMAP_TAG_VERSION_STR_CONFIG("boot-mode", "normal"),
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{ }
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};
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static char *boot_reason_ptr;
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static char *hw_build_ptr;
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static char *nolo_version_ptr;
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static char *boot_mode_ptr;
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static int serial_was_console_enabled;
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/*
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* Routine: init_omap_tags
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* Description: Initialize pointers to values in tag_omap
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*/
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static void init_omap_tags(void)
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{
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char *component;
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char *version;
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int i = 0;
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while (omap[i].hdr.tag) {
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switch (omap[i].hdr.tag) {
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case OMAP_TAG_BOOT_REASON:
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boot_reason_ptr = omap[i].u.boot_reason.reason_str;
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break;
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case OMAP_TAG_VERSION_STR:
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component = omap[i].u.version.component;
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version = omap[i].u.version.version;
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if (strcmp(component, "hw-build") == 0)
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hw_build_ptr = version;
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else if (strcmp(component, "nolo") == 0)
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nolo_version_ptr = version;
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else if (strcmp(component, "boot-mode") == 0)
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boot_mode_ptr = version;
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break;
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default:
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break;
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}
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i++;
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}
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}
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static void reuse_omap_atags(struct tag_omap *t)
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{
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char *component;
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char *version;
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while (t->hdr.tag) {
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switch (t->hdr.tag) {
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case OMAP_TAG_BOOT_REASON:
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memset(boot_reason_ptr, 0, 12);
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strcpy(boot_reason_ptr, t->u.boot_reason.reason_str);
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break;
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case OMAP_TAG_VERSION_STR:
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component = t->u.version.component;
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version = t->u.version.version;
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if (strcmp(component, "hw-build") == 0) {
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memset(hw_build_ptr, 0, 12);
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strcpy(hw_build_ptr, version);
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} else if (strcmp(component, "nolo") == 0) {
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memset(nolo_version_ptr, 0, 12);
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strcpy(nolo_version_ptr, version);
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} else if (strcmp(component, "boot-mode") == 0) {
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memset(boot_mode_ptr, 0, 12);
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strcpy(boot_mode_ptr, version);
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}
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break;
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case OMAP_TAG_UART:
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if (t->u.uart.enabled_uarts)
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serial_was_console_enabled = 1;
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break;
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case OMAP_TAG_SERIAL_CONSOLE:
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serial_was_console_enabled = 1;
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break;
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default:
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break;
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}
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t = tag_omap_next(t);
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}
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}
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/*
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* Routine: reuse_atags
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* Description: Reuse atags from previous bootloader.
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* Reuse only only HW build, boot reason, boot mode and nolo
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*/
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static void reuse_atags(void)
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{
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struct tag *t = (struct tag *)gd->bd->bi_boot_params;
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/* First tag must be ATAG_CORE */
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if (t->hdr.tag != ATAG_CORE)
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return;
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if (!boot_reason_ptr || !hw_build_ptr)
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return;
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/* Last tag must be ATAG_NONE */
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while (t->hdr.tag != ATAG_NONE) {
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switch (t->hdr.tag) {
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case ATAG_REVISION:
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memset(hw_build_ptr, 0, 12);
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sprintf(hw_build_ptr, "%x", t->u.revision.rev);
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break;
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case ATAG_BOARD:
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reuse_omap_atags((struct tag_omap *)&t->u);
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break;
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default:
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break;
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}
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t = tag_next(t);
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}
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}
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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#if defined(CONFIG_CMD_ONENAND)
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const u32 gpmc_regs_onenandrx51[GPMC_MAX_REG] = {
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ONENAND_GPMC_CONFIG1_RX51,
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ONENAND_GPMC_CONFIG2_RX51,
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ONENAND_GPMC_CONFIG3_RX51,
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ONENAND_GPMC_CONFIG4_RX51,
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ONENAND_GPMC_CONFIG5_RX51,
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ONENAND_GPMC_CONFIG6_RX51,
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0
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};
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#endif
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/* in SRAM or SDRAM, finish GPMC */
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gpmc_init();
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#if defined(CONFIG_CMD_ONENAND)
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enable_gpmc_cs_config(gpmc_regs_onenandrx51, &gpmc_cfg->cs[0],
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CFG_SYS_ONENAND_BASE, GPMC_SIZE_256M);
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#endif
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/* Enable the clks & power */
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per_clocks_enable();
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/* boot param addr */
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gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100;
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return 0;
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}
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#ifdef CONFIG_REVISION_TAG
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/*
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* Routine: get_board_revision
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* Description: Return board revision.
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*/
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u32 get_board_rev(void)
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{
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return simple_strtol(hw_build_ptr, NULL, 16);
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}
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#endif
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/*
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* Routine: setup_board_tags
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* Description: Append board specific boot tags.
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*/
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void setup_board_tags(struct tag **in_params)
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{
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int setup_console_atag;
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char *setup_boot_reason_atag;
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char *setup_boot_mode_atag;
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char *str;
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int i;
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int size;
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int total_size;
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struct tag *params;
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struct tag_omap *t;
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params = (struct tag *)gd->bd->bi_boot_params;
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params->u.core.flags = 0x0;
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params->u.core.pagesize = 0x1000;
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params->u.core.rootdev = 0x0;
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/* append omap atag only if env setup_omap_atag is set to 1 */
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str = env_get("setup_omap_atag");
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if (!str || str[0] != '1')
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return;
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str = env_get("setup_console_atag");
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if (str && str[0]) {
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if (str[0] == '1')
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setup_console_atag = 1;
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else
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setup_console_atag = 0;
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} else {
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if (serial_was_console_enabled)
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setup_console_atag = 1;
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else
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setup_console_atag = 0;
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}
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setup_boot_reason_atag = env_get("setup_boot_reason_atag");
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setup_boot_mode_atag = env_get("setup_boot_mode_atag");
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params = *in_params;
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t = (struct tag_omap *)¶ms->u;
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total_size = sizeof(struct tag_header);
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for (i = 0; omap[i].hdr.tag; i++) {
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/* skip serial console tag */
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if (!setup_console_atag &&
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omap[i].hdr.tag == OMAP_TAG_SERIAL_CONSOLE)
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continue;
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size = omap[i].hdr.size + sizeof(struct tag_omap_header);
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memcpy(t, &omap[i], size);
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/* set uart tag to 0 - disable serial console */
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if (!setup_console_atag && omap[i].hdr.tag == OMAP_TAG_UART)
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t->u.uart.enabled_uarts = 0;
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/* change boot reason */
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if (setup_boot_reason_atag &&
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omap[i].hdr.tag == OMAP_TAG_BOOT_REASON) {
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memset(t->u.boot_reason.reason_str, 0, 12);
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strcpy(t->u.boot_reason.reason_str,
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setup_boot_reason_atag);
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}
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/* change boot mode */
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if (setup_boot_mode_atag &&
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omap[i].hdr.tag == OMAP_TAG_VERSION_STR &&
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strcmp(omap[i].u.version.component, "boot-mode") == 0) {
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memset(t->u.version.version, 0, 12);
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strcpy(t->u.version.version, setup_boot_mode_atag);
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}
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total_size += size;
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t = tag_omap_next(t);
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}
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params->hdr.tag = ATAG_BOARD;
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params->hdr.size = total_size >> 2;
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params = tag_next(params);
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*in_params = params;
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}
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static int rx51_video_probe(struct udevice *dev)
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{
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struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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uc_plat->base = 0x8f9c0000;
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uc_plat->size = 800 * 480 * sizeof(u16);
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uc_priv->xsize = 800;
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uc_priv->ysize = 480;
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uc_priv->bpix = VIDEO_BPP16;
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video_set_flush_dcache(dev, true);
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return 0;
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}
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U_BOOT_DRIVER(rx51_video) = {
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.name = "rx51_video",
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.id = UCLASS_VIDEO,
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.probe = rx51_video_probe,
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};
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/*
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* Routine: twl4030_regulator_set_mode
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* Description: Set twl4030 regulator mode over i2c powerbus.
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*/
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static void twl4030_regulator_set_mode(u8 id, u8 mode)
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{
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u16 msg = MSG_SINGULAR(DEV_GRP_P1, id, mode);
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twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
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TWL4030_PM_MASTER_PB_WORD_MSB, msg >> 8);
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twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
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TWL4030_PM_MASTER_PB_WORD_LSB, msg & 0xff);
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}
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static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
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{
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u32 i, num_params = *parameters;
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u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
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/*
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* copy the parameters to an un-cached area to avoid coherency
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* issues
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*/
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for (i = 0; i < num_params; i++) {
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__raw_writel(*parameters, sram_scratch_space);
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parameters++;
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sram_scratch_space++;
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}
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/* Now make the PPA call */
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do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
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}
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void omap3_set_aux_cr_secure(u32 acr)
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{
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struct emu_hal_params_rx51 emu_romcode_params = { 0, };
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emu_romcode_params.num_params = 2;
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emu_romcode_params.param1 = acr;
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omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
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(u32 *)&emu_romcode_params);
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}
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/*
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* Routine: omap3_update_aux_cr_secure_rx51
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* Description: Modify the contents Auxiliary Control Register.
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* Parameters:
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* set_bits - bits to set in ACR
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* clr_bits - bits to clear in ACR
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*/
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static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits)
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{
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u32 acr;
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/* Read ACR */
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asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
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acr &= ~clear_bits;
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acr |= set_bits;
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omap3_set_aux_cr_secure(acr);
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}
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/*
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* Routine: misc_init_r
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* Description: Configure board specific parts.
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*/
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int misc_init_r(void)
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{
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struct udevice *dev;
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char buf[12];
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u8 state;
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/* disable lp5523 led */
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if (i2c_get_chip_for_busnum(1, 0x32, 1, &dev) == 0)
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dm_i2c_reg_write(dev, 0x00, 0x00);
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/* initialize twl4030 power managment */
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twl4030_power_init();
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twl4030_power_mmc_init(0);
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twl4030_power_mmc_init(1);
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/* set VSIM to 1.8V */
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twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
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TWL4030_PM_RECEIVER_VSIM_VSEL_18,
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TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
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TWL4030_PM_RECEIVER_DEV_GRP_P1);
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/* store I2C access state */
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twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
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&state);
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/* enable I2C access to powerbus (needed for twl4030 regulator) */
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twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
|
|
0x02);
|
|
|
|
/* set VAUX3, VSIM and VMMC1 state to active - enable eMMC memory */
|
|
twl4030_regulator_set_mode(RES_VAUX3, RES_STATE_ACTIVE);
|
|
twl4030_regulator_set_mode(RES_VSIM, RES_STATE_ACTIVE);
|
|
twl4030_regulator_set_mode(RES_VMMC1, RES_STATE_ACTIVE);
|
|
|
|
/* restore I2C access state */
|
|
twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
|
|
state);
|
|
|
|
/* set env variable attkernaddr for relocated kernel */
|
|
sprintf(buf, "%#x", KERNEL_ADDRESS);
|
|
env_set("attkernaddr", buf);
|
|
|
|
/* initialize omap tags */
|
|
init_omap_tags();
|
|
|
|
/* reuse atags from previous bootloader */
|
|
reuse_atags();
|
|
|
|
omap_die_id_display();
|
|
print_cpuinfo();
|
|
|
|
/*
|
|
* Cortex-A8(r1p0..r1p2) errata 430973 workaround
|
|
* Set IBE bit in Auxiliary Control Register
|
|
*
|
|
* Call this routine only on real secure device
|
|
* Qemu does not implement secure PPA and crash
|
|
*/
|
|
if (get_device_type() == HS_DEVICE)
|
|
omap3_update_aux_cr_secure_rx51(1 << 6, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned long int twl_wd_time; /* last time of watchdog reset */
|
|
static unsigned long int twl_i2c_lock;
|
|
|
|
/*
|
|
* Routine: rx51_watchdog_reset
|
|
* Description: Reset timeout of twl4030 watchdog.
|
|
*/
|
|
static int rx51_watchdog_reset(struct udevice *dev)
|
|
{
|
|
u8 timeout = 0;
|
|
|
|
/* do not reset watchdog too often - max every 4s */
|
|
if (get_timer(twl_wd_time) < 4 * CONFIG_SYS_HZ)
|
|
return 0;
|
|
|
|
/* localy lock twl4030 i2c bus */
|
|
if (test_and_set_bit(0, &twl_i2c_lock))
|
|
return 0;
|
|
|
|
/* read actual watchdog timeout */
|
|
twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER,
|
|
TWL4030_PM_RECEIVER_WATCHDOG_CFG, &timeout);
|
|
|
|
/* timeout 0 means watchdog is disabled */
|
|
/* reset watchdog timeout to 31s (maximum) */
|
|
if (timeout != 0)
|
|
twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
|
|
TWL4030_PM_RECEIVER_WATCHDOG_CFG, 31);
|
|
|
|
/* store last watchdog reset time */
|
|
twl_wd_time = get_timer(0);
|
|
|
|
/* localy unlock twl4030 i2c bus */
|
|
test_and_clear_bit(0, &twl_i2c_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rx51_watchdog_start(struct udevice *dev, u64 timeout_ms, ulong flags)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int rx51_watchdog_probe(struct udevice *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static const struct wdt_ops rx51_watchdog_ops = {
|
|
.start = rx51_watchdog_start,
|
|
.reset = rx51_watchdog_reset,
|
|
};
|
|
|
|
U_BOOT_DRIVER(rx51_watchdog) = {
|
|
.name = "rx51_watchdog",
|
|
.id = UCLASS_WDT,
|
|
.ops = &rx51_watchdog_ops,
|
|
.probe = rx51_watchdog_probe,
|
|
};
|
|
|
|
/*
|
|
* TWL4030 keypad handler for cfb_console
|
|
*/
|
|
|
|
static const char keymap[] = {
|
|
/* normal */
|
|
'q', 'o', 'p', ',', '\b', 0, 'a', 's',
|
|
'w', 'd', 'f', 'g', 'h', 'j', 'k', 'l',
|
|
'e', '.', 0, '\r', 0, 'z', 'x', 'c',
|
|
'r', 'v', 'b', 'n', 'm', ' ', 0, 0,
|
|
't', 0, 0, 0, 0, 0, 0, 0,
|
|
'y', 0, 0, 0, 0, 0, 0, 0,
|
|
'u', 0, 0, 0, 0, 0, 0, 0,
|
|
'i', 5, 6, 0, 0, 0, 0, 0,
|
|
/* fn */
|
|
'1', '9', '0', '=', '\b', 0, '*', '+',
|
|
'2', '#', '-', '_', '(', ')', '&', '!',
|
|
'3', '?', '^', '\r', 0, 156, '$', 238,
|
|
'4', '/', '\\', '"', '\'', '@', 0, '<',
|
|
'5', '|', '>', 0, 0, 0, 0, 0,
|
|
'6', 0, 0, 0, 0, 0, 0, 0,
|
|
'7', 0, 0, 0, 0, 0, 0, 0,
|
|
'8', 16, 17, 0, 0, 0, 0, 0,
|
|
};
|
|
|
|
static u8 keys[8];
|
|
static u8 old_keys[8] = {0, 0, 0, 0, 0, 0, 0, 0};
|
|
#define KEYBUF_SIZE 32
|
|
static u8 keybuf[KEYBUF_SIZE];
|
|
static u8 keybuf_head;
|
|
static u8 keybuf_tail;
|
|
|
|
/*
|
|
* Routine: rx51_kp_start
|
|
* Description: Initialize HW keyboard.
|
|
*/
|
|
static int rx51_kp_start(struct udevice *dev)
|
|
{
|
|
int ret = 0;
|
|
u8 ctrl;
|
|
ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD,
|
|
TWL4030_KEYPAD_KEYP_CTRL_REG, &ctrl);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* turn on keyboard and use hardware scanning */
|
|
ctrl |= TWL4030_KEYPAD_CTRL_KBD_ON;
|
|
ctrl |= TWL4030_KEYPAD_CTRL_SOFT_NRST;
|
|
ctrl |= TWL4030_KEYPAD_CTRL_SOFTMODEN;
|
|
ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
|
|
TWL4030_KEYPAD_KEYP_CTRL_REG, ctrl);
|
|
/* enable key event status */
|
|
ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
|
|
TWL4030_KEYPAD_KEYP_IMR1, 0xfe);
|
|
/* enable interrupt generation on rising and falling */
|
|
/* this is a workaround for qemu twl4030 emulation */
|
|
ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
|
|
TWL4030_KEYPAD_KEYP_EDR, 0x57);
|
|
/* enable ISR clear on read */
|
|
ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
|
|
TWL4030_KEYPAD_KEYP_SIH_CTRL, 0x05);
|
|
return 0;
|
|
}
|
|
|
|
static void rx51_kp_fill(u8 k, u8 mods)
|
|
{
|
|
/* check if some cursor key without meta fn key was pressed */
|
|
if (!(mods & 2) && (k == 18 || k == 31 || k == 33 || k == 34)) {
|
|
keybuf[keybuf_tail++] = '\e';
|
|
keybuf_tail %= KEYBUF_SIZE;
|
|
keybuf[keybuf_tail++] = '[';
|
|
keybuf_tail %= KEYBUF_SIZE;
|
|
if (k == 18) /* up */
|
|
keybuf[keybuf_tail++] = 'A';
|
|
else if (k == 31) /* left */
|
|
keybuf[keybuf_tail++] = 'D';
|
|
else if (k == 33) /* down */
|
|
keybuf[keybuf_tail++] = 'B';
|
|
else if (k == 34) /* right */
|
|
keybuf[keybuf_tail++] = 'C';
|
|
keybuf_tail %= KEYBUF_SIZE;
|
|
return;
|
|
}
|
|
|
|
if (mods & 2) { /* fn meta key was pressed */
|
|
k = keymap[k+64];
|
|
} else {
|
|
k = keymap[k];
|
|
if (mods & 1) { /* ctrl key was pressed */
|
|
if (k >= 'a' && k <= 'z')
|
|
k -= 'a' - 1;
|
|
}
|
|
if (mods & 4) { /* shift key was pressed */
|
|
if (k >= 'a' && k <= 'z')
|
|
k += 'A' - 'a';
|
|
else if (k == '.')
|
|
k = ':';
|
|
else if (k == ',')
|
|
k = ';';
|
|
}
|
|
}
|
|
keybuf[keybuf_tail++] = k;
|
|
keybuf_tail %= KEYBUF_SIZE;
|
|
}
|
|
|
|
/*
|
|
* Routine: rx51_kp_tstc
|
|
* Description: Test if key was pressed (from buffer).
|
|
*/
|
|
static int rx51_kp_tstc(struct udevice *dev)
|
|
{
|
|
u8 c, r, dk, i;
|
|
u8 intr;
|
|
u8 mods;
|
|
|
|
/* localy lock twl4030 i2c bus */
|
|
if (test_and_set_bit(0, &twl_i2c_lock))
|
|
return 0;
|
|
|
|
/* twl4030 remembers up to 2 events */
|
|
for (i = 0; i < 2; i++) {
|
|
|
|
/* check interrupt register for events */
|
|
twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD,
|
|
TWL4030_KEYPAD_KEYP_ISR1 + (2 * i), &intr);
|
|
|
|
/* no event */
|
|
if (!(intr&1))
|
|
continue;
|
|
|
|
/* read the key state */
|
|
twl4030_i2c_read(TWL4030_CHIP_KEYPAD,
|
|
TWL4030_KEYPAD_FULL_CODE_7_0, keys, 8);
|
|
|
|
/* cut out modifier keys from the keystate */
|
|
mods = keys[4] >> 4;
|
|
keys[4] &= 0x0f;
|
|
|
|
/* space key is indicated by two different bits */
|
|
keys[3] |= (keys[3] & (1 << 6)) >> 1;
|
|
keys[3] &= ~(1 << 6);
|
|
|
|
for (c = 0; c < 8; c++) {
|
|
|
|
/* get newly pressed keys only */
|
|
dk = ((keys[c] ^ old_keys[c])&keys[c]);
|
|
old_keys[c] = keys[c];
|
|
|
|
/* fill the keybuf */
|
|
for (r = 0; r < 8; r++) {
|
|
if (dk&1)
|
|
rx51_kp_fill((c*8)+r, mods);
|
|
dk = dk >> 1;
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* localy unlock twl4030 i2c bus */
|
|
test_and_clear_bit(0, &twl_i2c_lock);
|
|
|
|
return (KEYBUF_SIZE + keybuf_tail - keybuf_head)%KEYBUF_SIZE;
|
|
}
|
|
|
|
/*
|
|
* Routine: rx51_kp_getc
|
|
* Description: Get last pressed key (from buffer).
|
|
*/
|
|
static int rx51_kp_getc(struct udevice *dev)
|
|
{
|
|
keybuf_head %= KEYBUF_SIZE;
|
|
while (!rx51_kp_tstc(dev))
|
|
schedule();
|
|
return keybuf[keybuf_head++];
|
|
}
|
|
|
|
static int rx51_kp_probe(struct udevice *dev)
|
|
{
|
|
struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev);
|
|
struct stdio_dev *sdev = &uc_priv->sdev;
|
|
|
|
strcpy(sdev->name, "keyboard");
|
|
return input_stdio_register(sdev);
|
|
}
|
|
|
|
static const struct keyboard_ops rx51_kp_ops = {
|
|
.start = rx51_kp_start,
|
|
.tstc = rx51_kp_tstc,
|
|
.getc = rx51_kp_getc,
|
|
};
|
|
|
|
U_BOOT_DRIVER(rx51_kp) = {
|
|
.name = "rx51_kp",
|
|
.id = UCLASS_KEYBOARD,
|
|
.probe = rx51_kp_probe,
|
|
.ops = &rx51_kp_ops,
|
|
};
|
|
|
|
static const struct mmc_config rx51_mmc_cfg = {
|
|
.host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS,
|
|
.f_min = 400000,
|
|
.f_max = 52000000,
|
|
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
|
|
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
|
|
};
|
|
|
|
static const struct omap_hsmmc_plat rx51_mmc[] = {
|
|
{ rx51_mmc_cfg, (struct hsmmc *)OMAP_HSMMC1_BASE },
|
|
{ rx51_mmc_cfg, (struct hsmmc *)OMAP_HSMMC2_BASE },
|
|
};
|
|
|
|
U_BOOT_DRVINFOS(rx51_mmc) = {
|
|
{ "omap_hsmmc", &rx51_mmc[0] },
|
|
{ "omap_hsmmc", &rx51_mmc[1] },
|
|
};
|
|
|
|
static const struct omap_i2c_plat rx51_i2c[] = {
|
|
{ I2C_BASE1, 100000, OMAP_I2C_REV_V1 },
|
|
{ I2C_BASE2, 100000, OMAP_I2C_REV_V1 },
|
|
{ I2C_BASE3, 100000, OMAP_I2C_REV_V1 },
|
|
};
|
|
|
|
U_BOOT_DRVINFOS(rx51_i2c) = {
|
|
{ "i2c_omap", &rx51_i2c[0] },
|
|
{ "i2c_omap", &rx51_i2c[1] },
|
|
{ "i2c_omap", &rx51_i2c[2] },
|
|
};
|
|
|
|
U_BOOT_DRVINFOS(rx51_watchdog) = {
|
|
{ "rx51_watchdog" },
|
|
};
|
|
|
|
U_BOOT_DRVINFOS(rx51_video) = {
|
|
{ "rx51_video" },
|
|
};
|
|
|
|
U_BOOT_DRVINFOS(rx51_kp) = {
|
|
{ "rx51_kp" },
|
|
};
|
|
|
|
static const struct ns16550_plat rx51_serial = {
|
|
.base = CFG_SYS_NS16550_COM3,
|
|
.reg_shift = 2,
|
|
.clock = CFG_SYS_NS16550_CLK,
|
|
.fcr = UART_FCR_DEFVAL,
|
|
};
|
|
|
|
U_BOOT_DRVINFOS(rx51_uart) = {
|
|
{ "omap_serial", &rx51_serial },
|
|
};
|