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aa6e94deab
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
200 lines
4.5 KiB
C
200 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l
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*/
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#include <common.h>
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#include <init.h>
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#include <serial.h>
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#include <watchdog.h>
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#include <command.h>
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#include <asm/global_data.h>
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#include <asm/m5329.h>
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#include <asm/immap_5329.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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/* needed for astro bus: */
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#include <asm/uart.h>
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#include "astro.h"
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DECLARE_GLOBAL_DATA_PTR;
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extern void uart_port_conf(void);
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int checkboard(void)
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{
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puts("Board: ");
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puts("ASTRO MCF5373L (Urmel) Board\n");
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return 0;
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}
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int dram_init(void)
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{
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#if !defined(CONFIG_MONITOR_IS_IN_RAM)
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sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
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/*
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* GPIO configuration for bus should be set correctly from reset,
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* so we do not care! First, set up address space: at this point,
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* we should be running from internal SRAM;
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* so use CFG_SYS_SDRAM_BASE as the base address for SDRAM,
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* and do not care where it is
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*/
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__raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
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&sdp->cs0);
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__raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
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&sdp->cs1);
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/*
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* I am not sure from the data sheet, but it seems burst length
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* has to be 8 for the 16 bit data bus we use;
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* so these values are for BL = 8
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*/
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__raw_writel(0x33211530, &sdp->cfg1);
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__raw_writel(0x56570000, &sdp->cfg2);
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/* send PrechargeALL, REF and IREF remain cleared! */
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__raw_writel(0xE1462C02, &sdp->ctrl);
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udelay(1);
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/* refresh SDRAM twice */
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__raw_writel(0xE1462C04, &sdp->ctrl);
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udelay(1);
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__raw_writel(0xE1462C04, &sdp->ctrl);
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/* init MR */
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__raw_writel(0x008D0000, &sdp->mode);
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/* initialize EMR */
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__raw_writel(0x80010000, &sdp->mode);
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/* wait until DLL is locked */
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udelay(1);
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/*
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* enable automatic refresh, lock mode register,
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* clear iref and ipall
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*/
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__raw_writel(0x71462C00, &sdp->ctrl);
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/* Dummy write to start SDRAM */
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writel(0, CFG_SYS_SDRAM_BASE);
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#endif
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/*
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* for get_ram_size() to work, both CS areas have to be
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* configured, i.e. CS1 has to be explicitely disabled, else
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* probing for memory will cause the SDRAM bus to hang!
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* (Do not rely on the SDCS register(s) being set to 0x00000000
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* during reset as stated in the data sheet.)
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*/
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gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
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0x80000000 - CFG_SYS_SDRAM_BASE);
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return 0;
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}
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#define UART_BASE MMAP_UART0
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int rs_serial_init(int port, int baud)
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{
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uart_t *uart;
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u32 counter;
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switch (port) {
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case 0:
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uart = (uart_t *)(MMAP_UART0);
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break;
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case 1:
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uart = (uart_t *)(MMAP_UART1);
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break;
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case 2:
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uart = (uart_t *)(MMAP_UART2);
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break;
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default:
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uart = (uart_t *)(MMAP_UART0);
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}
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uart_port_conf();
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/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
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writeb(UART_UCR_RESET_RX, &uart->ucr);
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writeb(UART_UCR_RESET_TX, &uart->ucr);
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writeb(UART_UCR_RESET_ERROR, &uart->ucr);
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writeb(UART_UCR_RESET_MR, &uart->ucr);
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__asm__ ("nop");
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writeb(0, &uart->uimr);
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/* write to CSR: RX/TX baud rate from timers */
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writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
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writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
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writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
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/* Setting up BaudRate */
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counter = (u32) (gd->bus_clk / (baud));
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counter >>= 5;
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/* write to CTUR: divide counter upper byte */
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writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1);
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/* write to CTLR: divide counter lower byte */
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writeb((u8) (counter & 0x00ff), &uart->ubg2);
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writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
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return 0;
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}
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void astro_put_char(char ch)
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{
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uart_t *uart;
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unsigned long timer;
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uart = (uart_t *)(MMAP_UART0);
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/*
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* Wait for last character to go. Timeout of 6ms should
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* be enough for our lowest baud rate of 2400.
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*/
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timer = get_timer(0);
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while (get_timer(timer) < 6) {
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if (readb(&uart->usr) & UART_USR_TXRDY)
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break;
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}
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writeb(ch, &uart->utb);
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return;
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}
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int astro_is_char(void)
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{
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uart_t *uart;
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uart = (uart_t *)(MMAP_UART0);
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return readb(&uart->usr) & UART_USR_RXRDY;
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}
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int astro_get_char(void)
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{
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uart_t *uart;
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uart = (uart_t *)(MMAP_UART0);
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while (!(readb(&uart->usr) & UART_USR_RXRDY)) ;
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return readb(&uart->urb);
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}
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int misc_init_r(void)
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{
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int retval = 0;
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puts("Configure Xilinx FPGA...");
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retval = astro5373l_xilinx_load();
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if (!retval) {
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puts("failed!\n");
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return retval;
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}
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puts("done\n");
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puts("Configure Altera FPGA...");
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retval = astro5373l_altera_load();
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if (!retval) {
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puts("failed!\n");
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return retval;
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}
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puts("done\n");
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return retval;
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}
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