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SPARC has implemented __raw_readq, it reads 64-bit from any 32-bit address. SPARC CPUs implement flash_read64 which calls __raw_readq. For current SPARC architectures (LEON2 and LEON3) each read from the FLASH must lead to a cache miss. This is because FLASH can not be set non-cacheable since program code resides there, and alternatively disabling cache is poor from performance view, or doing a cache flush between each read is even poorer. Forcing a cache miss on a SPARC is done by a special instruction "lda" - load alternative space, the alternative space number (ASI) is processor implementation spcific and can be found by including <asm/processor.h>. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> |
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bios_emulator | ||
block | ||
dma | ||
hwmon | ||
i2c | ||
input | ||
misc | ||
mtd | ||
net | ||
pci | ||
pcmcia | ||
qe | ||
rtc | ||
serial | ||
spi | ||
usb | ||
video |