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443ce4ac9d
With these fixes, this driver works properly for multi chip addressging mode Bugfixes: 1. Build error fixed for function mv88e61xx_busychk_multic-fixed 2. PHY dev address error detection- fixed 3. wrong busy bit was refered in function mv88e61xx_busychk -fixed 4. invalid data read ptr was refered for RD_PHY in case of multichip addressing mode -fixed The Multichip Address mode is tested with RD6281A board having MV88E6165 switch on it Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
413 lines
11 KiB
C
413 lines
11 KiB
C
/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include "mv88e61xx.h"
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#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
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/* Chip Address mode
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* The Switch support two modes of operation
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* 1. single chip mode and
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* 2. Multi-chip mode
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* Refer section 9.2 &9.3 in chip datasheet-02 for more details
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*
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* By default single chip mode is configured
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* multichip mode operation can be configured in board header
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*/
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static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
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{
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u32 reg = 0;
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u32 timeout = MV88E61XX_PHY_TIMEOUT;
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/* Poll till SMIBusy bit is clear */
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do {
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miiphy_read(name, devaddr, 0x0, ®);
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if (timeout-- == 0) {
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printf("SMI busy timeout\n");
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return -1;
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}
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} while (reg & (1 << 15));
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return 0;
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}
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static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data)
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{
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u16 reg;
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u32 mii_dev_addr;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
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printf("Error..could not read PHY dev address\n");
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return;
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}
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mv88e61xx_busychk_multic(name, mii_dev_addr);
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/* Write data to Switch indirect data register */
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miiphy_write(name, mii_dev_addr, 0x1, data);
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/* Write command to Switch indirect command register (write) */
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miiphy_write(name, mii_dev_addr, 0x0,
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reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 <<
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15));
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}
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static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data)
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{
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u16 reg;
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u32 mii_dev_addr;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
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printf("Error..could not read PHY dev address\n");
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return;
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}
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mv88e61xx_busychk_multic(name, mii_dev_addr);
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/* Write command to Switch indirect command register (read) */
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miiphy_write(name, mii_dev_addr, 0x0,
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reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 <<
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15));
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mv88e61xx_busychk_multic(name, mii_dev_addr);
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/* Read data from Switch indirect data register */
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miiphy_read(name, mii_dev_addr, 0x1, data);
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}
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#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
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static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig,
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u32 max_prtnum, u32 ports_ofs)
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{
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u32 prt;
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u16 reg;
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char *name = swconfig->name;
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u32 cpu_port = swconfig->cpuport;
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u32 port_mask = swconfig->ports_enabled;
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enum mv88e61xx_cfg_vlan vlancfg = swconfig->vlancfg;
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/* be sure all ports are disabled */
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for (prt = 0; prt < max_prtnum; prt++) {
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RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, ®);
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reg &= ~0x3;
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WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, reg);
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if (!(cpu_port & (1 << prt)))
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continue;
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/* Set CPU port VID to 0x1 */
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RD_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, ®);
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reg &= ~0xfff;
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reg |= 0x1;
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WR_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, reg);
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}
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/* Setting Port default priority for all ports to zero */
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for (prt = 0; prt < max_prtnum; prt++) {
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RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, ®);
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reg &= ~0xc000;
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WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, reg);
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}
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/* Setting VID and VID map for all ports except CPU port */
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for (prt = 0; prt < max_prtnum; prt++) {
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/* only for enabled ports */
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if ((1 << prt) & port_mask) {
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/* skip CPU port */
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if ((1 << prt) & cpu_port) {
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/*
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* Set Vlan map table for cpu_port to see
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* all ports
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*/
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RD_PHY(name, (ports_ofs + prt),
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MV88E61XX_PRT_VMAP_REG, ®);
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reg &= ~((1 << max_prtnum) - 1);
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reg |= port_mask & ~(1 << prt);
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WR_PHY(name, (ports_ofs + prt),
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MV88E61XX_PRT_VMAP_REG, reg);
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} else {
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/*
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* set Ports VLAN Mapping.
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* port prt <--> cpu_port VLAN #prt+1.
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*/
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RD_PHY(name, ports_ofs + prt,
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MV88E61XX_PRT_VID_REG, ®);
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reg &= ~0x0fff;
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reg |= (prt + 1);
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WR_PHY(name, ports_ofs + prt,
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MV88E61XX_PRT_VID_REG, reg);
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RD_PHY(name, ports_ofs + prt,
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MV88E61XX_PRT_VMAP_REG, ®);
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if (vlancfg == MV88E61XX_VLANCFG_DEFAULT) {
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/*
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* all any port can send frames to all other ports
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* ref: sec 3.2.1.1 of datasheet
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*/
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reg |= 0x03f;
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reg &= ~(1 << prt);
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} else if (vlancfg == MV88E61XX_VLANCFG_ROUTER) {
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/*
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* all other ports can send frames to CPU port only
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* ref: sec 3.2.1.2 of datasheet
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*/
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reg &= ~((1 << max_prtnum) - 1);
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reg |= cpu_port;
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}
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WR_PHY(name, ports_ofs + prt,
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MV88E61XX_PRT_VMAP_REG, reg);
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}
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}
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}
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/*
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* enable only appropriate ports to forwarding mode
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* and disable the others
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*/
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for (prt = 0; prt < max_prtnum; prt++) {
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if ((1 << prt) & port_mask) {
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RD_PHY(name, ports_ofs + prt,
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MV88E61XX_PRT_CTRL_REG, ®);
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reg |= 0x3;
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WR_PHY(name, ports_ofs + prt,
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MV88E61XX_PRT_CTRL_REG, reg);
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} else {
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/* Disable port */
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RD_PHY(name, ports_ofs + prt,
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MV88E61XX_PRT_CTRL_REG, ®);
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reg &= ~0x3;
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WR_PHY(name, ports_ofs + prt,
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MV88E61XX_PRT_CTRL_REG, reg);
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}
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}
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}
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/*
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* Make sure SMIBusy bit cleared before another
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* SMI operation can take place
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*/
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static int mv88e61xx_busychk(char *name)
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{
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u32 reg = 0;
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u32 timeout = MV88E61XX_PHY_TIMEOUT;
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do {
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RD_PHY(name, MV88E61XX_GLB2REG_DEVADR,
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MV88E61XX_PHY_CMD, (u16 *) & reg);
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if (timeout-- == 0) {
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printf("SMI busy timeout\n");
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return -1;
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}
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} while (reg & 1 << 15); /* busy mask */
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return 0;
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}
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/*
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* Power up the specified port and reset PHY
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*/
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static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 prt)
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{
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char *name = swconfig->name;
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/* Write Copper Specific control reg1 (0x14) for-
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* Enable Phy power up
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* Energy Detect on (sense&Xmit NLP Periodically
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* reset other settings default
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*/
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WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x3360);
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WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
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MV88E61XX_PHY_CMD, (0x9410 | (prt << 5)));
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if (mv88e61xx_busychk(name))
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return -1;
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/* Write PHY ctrl reg (0x0) to apply
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* Phy reset (set bit 15 low)
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* reset other default values
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*/
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WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x1140);
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WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
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MV88E61XX_PHY_CMD, (0x9400 | (prt << 5)));
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if (mv88e61xx_busychk(name))
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return -1;
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return 0;
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}
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/*
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* Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3)
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* is set to "On-1000Mb/s Link, Off Else"
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* This function sets it to "On-Link, Blink-Activity, Off-NoLink"
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*
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* This is optional settings may be needed on some boards
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* to setup PHY LEDs default configuration to detect 10/100/1000Mb/s
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* Link status
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*/
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static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 prt)
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{
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char *name = swconfig->name;
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u16 reg;
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if (swconfig->led_init != MV88E61XX_LED_INIT_EN)
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return 0;
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/* set page address to 3 */
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reg = 3;
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WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
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WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
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MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
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1 << MV88E61XX_MODE_OFST |
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1 << MV88E61XX_OP_OFST |
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prt << MV88E61XX_ADDR_OFST | 22));
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if (mv88e61xx_busychk(name))
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return -1;
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/* set LED Func Ctrl reg */
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reg = 1; /* LED[0] On-Link, Blink-Activity, Off-NoLink */
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WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
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WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
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MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
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1 << MV88E61XX_MODE_OFST |
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1 << MV88E61XX_OP_OFST |
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prt << MV88E61XX_ADDR_OFST | 16));
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if (mv88e61xx_busychk(name))
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return -1;
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/* set page address to 0 */
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reg = 0;
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WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
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WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
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MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
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1 << MV88E61XX_MODE_OFST |
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1 << MV88E61XX_OP_OFST |
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prt << MV88E61XX_ADDR_OFST | 22));
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if (mv88e61xx_busychk(name))
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return -1;
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return 0;
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}
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/*
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* Reverse Transmit polarity for Media Dependent Interface
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* Pins (MDIP) bits in Copper Specific Control Register 3
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* (Page 0, Reg 20 for each phy (except cpu port)
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* Reference: Section 1.1 Switch datasheet-3
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*
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* This is optional settings may be needed on some boards
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* for PHY<->magnetics h/w tuning
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*/
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static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 prt)
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{
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char *name = swconfig->name;
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u16 reg;
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if (swconfig->mdip != MV88E61XX_MDIP_REVERSE)
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return 0;
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reg = 0x0f; /*Reverse MDIP/N[3:0] bits */
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WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
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WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
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MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
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1 << MV88E61XX_MODE_OFST |
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1 << MV88E61XX_OP_OFST |
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prt << MV88E61XX_ADDR_OFST | 20));
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if (mv88e61xx_busychk(name))
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return -1;
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return 0;
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}
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/*
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* Marvell 88E61XX Switch initialization
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*/
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int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
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{
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u32 prt;
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u16 reg;
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char *idstr;
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char *name = swconfig->name;
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if (miiphy_set_current_dev(name)) {
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printf("%s failed\n", __FUNCTION__);
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return -1;
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}
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if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) {
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swconfig->cpuport = (1 << 5);
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printf("Invalid cpu port config, using default port5\n");
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}
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RD_PHY(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, ®);
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reg &= 0xfff0;
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if (reg == 0x1610)
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idstr = "88E6161";
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if (reg == 0x1650)
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idstr = "88E6165";
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if (reg == 0x1210) {
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idstr = "88E6123";
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/* ports 2,3,4 not available */
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swconfig->ports_enabled &= 0x023;
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}
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/* Port based VLANs configuration */
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if ((swconfig->vlancfg == MV88E61XX_VLANCFG_DEFAULT)
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|| (swconfig->vlancfg == MV88E61XX_VLANCFG_ROUTER))
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mv88e61xx_port_vlan_config(swconfig, MV88E61XX_MAX_PORTS_NUM,
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MV88E61XX_PRT_OFST);
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else {
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printf("Unsupported mode %s failed\n", __FUNCTION__);
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return -1;
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}
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if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) {
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 9.5 of chip datasheet-02
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*/
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WR_PHY(name, MV88E61XX_PRT_OFST + 5,
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MV88E61XX_RGMII_TIMECTRL_REG, 0x18);
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WR_PHY(name, MV88E61XX_PRT_OFST + 4,
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MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
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}
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for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
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if (!((1 << prt) & swconfig->cpuport)) {
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if (mv88361xx_led_init(swconfig, prt))
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return -1;
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if (mv88361xx_reverse_mdipn(swconfig, prt))
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return -1;
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if (mv88361xx_powerup(swconfig, prt))
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return -1;
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}
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/*Program port state */
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RD_PHY(name, MV88E61XX_PRT_OFST + prt,
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MV88E61XX_PRT_CTRL_REG, ®);
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WR_PHY(name, MV88E61XX_PRT_OFST + prt,
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MV88E61XX_PRT_CTRL_REG,
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reg | (swconfig->portstate & 0x03));
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}
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printf("%s Initialized on %s\n", idstr, name);
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return 0;
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}
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