mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 13:56:30 +00:00
8f1a80e99e
Migrate all remaining instances of CMD_NAND, CMD_NAND_TRIMFFS CMD_NAND_LOCK_UNLOCK and CMD_NAND_TORTURE from the headers into the defconfig files. Tested-by: Adam Ford <aford173@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
255 lines
8.1 KiB
C
255 lines
8.1 KiB
C
/*
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* Configuration settings for the QUIPOS Cairo board.
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*
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* Copyright (C) DENX GmbH
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*
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* Author :
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* Albert ARIBAUD <albert.aribaud@3adev.fr>
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*
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* Derived from EVM code by
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* Manikandan Pillai <mani.pillai@ti.com>
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* Itself derived from Beagle Board and 3430 SDP code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* Also derived from include/configs/omap3_beagle.h
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __OMAP3_CAIRO_CONFIG_H
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#define __OMAP3_CAIRO_CONFIG_H
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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/*
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* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
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* 64 bytes before this address should be set aside for u-boot.img's
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* header. That is 0x800FFFC0--0x80100000 should not be used for any
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* other needs. We use this rather than the inherited defines from
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* ti_armv7_common.h for backwards compatibility.
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*/
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#define CONFIG_SYS_TEXT_BASE 0x80100000
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#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SPL_BSS_START_ADDR 0x80000000
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#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#define CONFIG_NAND
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#include <configs/ti_omap3_common.h>
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#define CONFIG_MISC_INIT_R
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#define CONFIG_REVISION_TAG 1
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#define CONFIG_ENV_OVERWRITE
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/* Enable Multi Bus support for I2C */
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#define CONFIG_I2C_MULTI_BUS 1
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/* Probe all devices */
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#define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} }
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#define CONFIG_NAND
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/*
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* TWL4030
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*/
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#define CONFIG_TWL4030_LED 1
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/*
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* Board NAND Info.
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*/
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"machid=ffffffff\0" \
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"fdt_high=0x87000000\0" \
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"baudrate=115200\0" \
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"fec_addr=00:50:C2:7E:90:F0\0" \
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"netmask=255.255.255.0\0" \
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"ipaddr=192.168.2.9\0" \
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"gateway=192.168.2.1\0" \
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"serverip=192.168.2.10\0" \
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"nfshost=192.168.2.10\0" \
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"stdin=serial\0" \
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"stdout=serial\0" \
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"stderr=serial\0" \
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"bootargs_mmc_ramdisk=mem=128M " \
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"console=ttyO1,115200n8 " \
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"root=/dev/ram0 rw " \
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"initrd=0x81600000,16M " \
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"mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
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"omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
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"mmcboot=mmc init; " \
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"fatload mmc 0 0x80000000 uImage; " \
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"fatload mmc 0 0x81600000 ramdisk.gz; " \
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"setenv bootargs ${bootargs_mmc_ramdisk}; " \
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"bootm 0x80000000\0" \
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"bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
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"root=/dev/nfs " \
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"nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
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"mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
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"omap_vout.vid1_static_vrfb_alloc=y\0" \
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"boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
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"bootm 0x80000000\0" \
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"bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
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"root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
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"omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
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"omapfb.rotate_type=1\0" \
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"boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
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"bootargs ${bootargs_nand}; bootm 0x80000000\0" \
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"ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
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"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
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"i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
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"ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
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"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
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"mw 60 09 00 1; i2c mw 60 06 10 1\0" \
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"ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
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"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
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"i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
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"ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
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"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
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"i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
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"flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
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"nand erase 0 20000; " \
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"fatload mmc 0 0x81600000 MLO; " \
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"nandecc hw; " \
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"nand write.i 0x81600000 0 20000;\0" \
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"flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
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"nand erase 80000 40000; " \
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"fatload mmc 0 0x81600000 u-boot.bin; " \
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"nandecc sw; " \
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"nand write.i 0x81600000 80000 40000;\0" \
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"flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
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"nand erase 280000 300000; " \
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"fatload mmc 0 0x81600000 uImage; " \
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"nandecc sw; " \
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"nand write.i 0x81600000 280000 300000;\0" \
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"flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
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"nandecc sw; " \
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"nand write.jffs2 0x680000 0xFF ${filesize}; " \
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"nand erase 680000 ${filesize}; " \
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"nand write.jffs2 81600000 680000 ${filesize};\0" \
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"flash_scrub=nand scrub; " \
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"run flash_xloader; " \
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"run flash_uboot; " \
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"run flash_kernel; " \
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"run flash_rootfs;\0" \
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"flash_all=run ledred; " \
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"nand erase.chip; " \
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"run ledorange; " \
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"run flash_xloader; " \
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"run flash_uboot; " \
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"run flash_kernel; " \
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"run flash_rootfs; " \
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"run ledgreen; " \
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"run boot_nand; \0" \
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#define CONFIG_BOOTCOMMAND \
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"if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
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"else run boot_nand; fi"
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/*
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* OMAP3 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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/* **** PISMO SUPPORT *** */
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#if defined(CONFIG_CMD_NAND)
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#define CONFIG_SYS_FLASH_BASE NAND_BASE
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#endif
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/* Monitor at start of flash */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
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#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
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#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
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#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
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#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
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#define CONFIG_OMAP3_SPI
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/* Defines for SPL */
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#define CONFIG_SPL_OMAP3_ID_NAND
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/* NAND boot config */
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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/* NAND: SPL falcon mode configs */
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#ifdef CONFIG_SPL_OS_BOOT
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#define CONFIG_CMD_SPL_NAND_OFS 0x240000
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#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
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#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
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#endif
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/* env defaults */
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#define CONFIG_BOOTFILE "uImage"
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/* Override OMAP3 common serial console configuration from UART3
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* to UART2.
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*
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* Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
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* are needed and peripheral clocks for UART2 must be enabled in
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* function per_clocks_enable().
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*/
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#undef CONFIG_CONS_INDEX
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#define CONFIG_CONS_INDEX 2
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#ifdef CONFIG_SPL_BUILD
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#undef CONFIG_SYS_NS16550_COM3
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#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2
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#undef CONFIG_SERIAL3
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#define CONFIG_SERIAL2
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#endif
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/* Provide the MACH_TYPE value the vendor kernel requires */
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#define CONFIG_MACH_TYPE 3063
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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/* **** PISMO SUPPORT *** */
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#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
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/* on one chip */
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
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/*-----------------------------------------------------------------------
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* CFI FLASH driver setup
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*/
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
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/* Flash banks JFFS2 should use */
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#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
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CONFIG_SYS_MAX_NAND_DEVICE)
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#define CONFIG_SYS_JFFS2_MEM_NAND
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/* use flash_info[2] */
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#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
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#define CONFIG_SYS_JFFS2_NUM_BANKS 1
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#endif /* __OMAP3_CAIRO_CONFIG_H */
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