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fe6293a809
Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
13 lines
290 B
C
13 lines
290 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Device Tree constants for the Qualcomm Atheros AR803x PHYs
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*/
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#ifndef _DT_BINDINGS_QCA_AR803X_H
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#define _DT_BINDINGS_QCA_AR803X_H
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#define AR803X_STRENGTH_FULL 0
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#define AR803X_STRENGTH_HALF 1
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#define AR803X_STRENGTH_QUARTER 2
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#endif
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