Lokesh Vutla 97405d843e ARM: DRA7xx: clocks: Update PLL values ... Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com>		2013-06-10 08:43:10 -04:00
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cpu	ARM: DRA7xx: clocks: Update PLL values	2013-06-10 08:43:10 -04:00
dts	EXYNOS5: Add device node for DP	2013-03-27 21:23:18 +09:00
imx-common	arm: vf610: Add IOMUX support for Vybrid VF610	2013-06-03 10:56:53 +02:00
include/asm	ARM: DRA7xx: clocks: Update PLL values	2013-06-10 08:43:10 -04:00
lib	arm: factorize relocate_code routine	2013-05-30 20:24:38 +02:00
config.mk	arm: Enable -ffunction-sections / -fdata-sections / --gc-sections	2013-05-23 12:09:56 +02:00