mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-15 09:27:35 +00:00
b60eff31f3
Remove the last uses of symbol offsets in ARM U-Boot. Remove some needless uses of _TEXT_BASE. Remove all _TEXT_BASE definitions. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
185 lines
4.4 KiB
ArmAsm
185 lines
4.4 KiB
ArmAsm
/*
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* armboot - Startup Code for ARM926EJS CPU-core
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*
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* Copyright (c) 2003 Texas Instruments
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*
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* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
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*
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* Copyright (c) 2001 Marius Groger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Zupke <azu@sysgo.de>
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* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (c) 2003 Kshitij <kshitij@ti.com>
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* Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
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*
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* Change to support call back into iMX28 bootrom
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* Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <common.h>
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#include <version.h>
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/*
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*************************************************************************
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*
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* Jump vector table as in table 3.1 in [1]
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*
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*************************************************************************
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*/
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.globl _start
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_start:
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b reset
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b undefined_instruction
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b software_interrupt
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b prefetch_abort
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b data_abort
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b not_used
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b irq
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b fiq
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/*
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* Vector table, located at address 0x20.
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* This table allows the code running AFTER SPL, the U-Boot, to install it's
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* interrupt handlers here. The problem is that the U-Boot is loaded into RAM,
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* including it's interrupt vectoring table and the table at 0x0 is still the
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* SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table
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* is still used.
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*/
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_vt_reset:
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.word _reset
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_vt_undefined_instruction:
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.word _hang
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_vt_software_interrupt:
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.word _hang
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_vt_prefetch_abort:
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.word _hang
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_vt_data_abort:
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.word _hang
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_vt_not_used:
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.word _reset
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_vt_irq:
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.word _hang
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_vt_fiq:
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.word _hang
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reset:
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ldr pc, _vt_reset
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undefined_instruction:
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ldr pc, _vt_undefined_instruction
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software_interrupt:
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ldr pc, _vt_software_interrupt
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prefetch_abort:
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ldr pc, _vt_prefetch_abort
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data_abort:
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ldr pc, _vt_data_abort
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not_used:
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ldr pc, _vt_not_used
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irq:
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ldr pc, _vt_irq
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fiq:
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ldr pc, _vt_fiq
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* setup Memory and board specific bits prior to relocation.
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* relocate armboot to ram
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* setup stack
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*
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*************************************************************************
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*/
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#ifdef CONFIG_USE_IRQ
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/* IRQ stack memory (calculated at run-time) */
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.globl IRQ_STACK_START
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IRQ_STACK_START:
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.word 0x0badc0de
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/* IRQ stack memory (calculated at run-time) */
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.globl FIQ_STACK_START
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FIQ_STACK_START:
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.word 0x0badc0de
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#endif
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/* IRQ stack memory (calculated at run-time) + 8 bytes */
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.globl IRQ_STACK_START_IN
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IRQ_STACK_START_IN:
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.word 0x0badc0de
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/*
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* the actual reset code
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*/
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_reset:
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/*
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* If the CPU is configured in "Wait JTAG connection mode", the stack
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* pointer is not configured and is zero. This will cause crash when
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* trying to push data onto stack right below here. Load the SP and make
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* it point to the end of OCRAM if the SP is zero.
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*/
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cmp sp, #0x00000000
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ldreq sp, =CONFIG_SYS_INIT_SP_ADDR
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/*
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* Store all registers on old stack pointer, this will allow us later to
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* return to the BootROM and let the BootROM load U-Boot into RAM.
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*
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* WARNING: Register r0 and r1 are used by the BootROM to pass data
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* to the called code. Register r0 will contain arbitrary
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* data that are set in the BootStream. In case this code
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* was started with CALL instruction, register r1 will contain
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* pointer to the return value this function can then set.
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* The code below MUST NOT CHANGE register r0 and r1 !
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*/
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push {r0-r12,r14}
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/* Save control register c1 */
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mrc p15, 0, r2, c1, c0, 0
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push {r2}
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/* Set the cpu to SVC32 mode and store old CPSR register content. */
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mrs r2, cpsr
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push {r2}
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bic r2, r2, #0x1f
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orr r2, r2, #0xd3
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msr cpsr, r2
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bl board_init_ll
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/* Restore BootROM's CPU mode (especially FIQ). */
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pop {r2}
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msr cpsr,r2
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/*
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* Restore c1 register. Especially set exception vector location
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* back to BootROM space which is required by bootrom for USB boot.
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*/
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pop {r2}
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mcr p15, 0, r2, c1, c0, 0
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pop {r0-r12,r14}
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/*
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* In case this code was started by the CALL instruction, the register
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* r0 is examined by the BootROM after this code returns. The value in
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* r0 must be set to 0 to indicate successful return.
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*/
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mov r0, #0
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bx lr
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_hang:
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1:
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bl 1b /* hang and never return */
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